Fast and accurate transaction-level model of a wormhole network-on-chip with priority preemptive virtual channel arbitration

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2011, Pages 1089-1094

  Indrusiak, Leandro Soares ^a   Dos Santos, Osmar Marchi ^a  

^a UNIVERSITY OF YORK   (United Kingdom)

Author keywords

network on chip; on chip multiprocessing; simulation; system specification; transaction level modeling

Indexed keywords

NETWORK ON CHIP; ON CHIPS; SIMULATION; SYSTEM SPECIFICATION; TRANSACTION LEVEL MODELING;

DESIGN; DISPENSERS; EMBEDDED SYSTEMS; INTERCONNECTION NETWORKS; MULTIPROCESSING SYSTEMS; ROUTERS; SERVERS; SPECIFICATIONS; VLSI CIRCUITS;

COMPUTER SIMULATION;

EID: 79957559929     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

1. Z. Shi, A. Burns, and L. S. Indrusiak, "Schedulability Analysis for Real Time On-Chip Communication with Wormhole Switching," International Journal of Embedded and Real-Time Communication Systems, vol. 1, no. 2, pp. 1 - 22, Jun. 2010.
2. N. Genko et al., "A novel approach for network on chip emulation," in Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on, pp. 2365-2368 Vol. 3, 2005.
3. J. Aynsley, "TLM-2.0 Language Reference Manual," OSCI, 2009.
4. G. Schirner and R. Dömer, "Quantitative analysis of the speed/accuracy trade-off in transaction level modeling," ACM Trans. Embed. Comput. Syst., vol. 8, no. 1, pp. 1-29, 2008.
5. Kai-Li Lin, Chen-Kang Lo, and Ren-Song Tsay, "Source-level timing annotation for fast and accurate TLM computation model generation," in Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific, pp. 235-240, 2010.
6. Ke Yu and N. Audsley, "A Mixed Timing System-Level Embedded Software Modelling and Simulation Approach," in Embedded Software and Systems, 2009. ICESS '09. International Conference on, pp. 193-200, 2009.
7. H. van Moll, H. Corporaal, V. Reyes, and M. Boonen, "Fast and accurate protocol specific bus modeling using TLM 2.0," in Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09., pp. 316-319, 2009.
8. G. Schirner and R. Dömer, "Result-Oriented Modeling-A Novel Technique for Fast and Accurate TLM," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 26, no. 9, pp. 1688-1699, 2007.
9. E. Viaud, F. Pêcheux, and A. Greiner, "An efficient TLM/T modeling and simulation environment based on conservative parallel discrete event principles," in Proceedings of the conference on Design, automation and test in Europe: Proceedings, pp. 94-99, 2006.
10. M. Hosseinabady and J. L. Nunez-Yanez, "SystemC Architectural Transaction Level Modelling for Large NoCs," in ECSI Forum on Specification and Design Languages (FDL), 2010.
11. P. K. McKinley and C. Trefftz, "MultiSim: A Simulation Tool for the Study of Large-Scale Multiprocessors," in Proceedings of the International Workshop on Modeling, Analysis, and Simulation On Computer and Telecommunication Systems, pp. 57-62, 1993.
12. L. Ost et al., "A simplified executable model to evaluate latency and throughput of networks-on-chip," in Proceedings of the 21st annual Symposium on Integrated Circuits and System Design, 2008.
13. A. Vieira de Mello, L. C. Ost, F. G. Moraes, and N. Calazans, Evaluation of Routing Algorithms on Mesh Based NoCs. Porto Alegre: Faculdade de Informatica - PUCRS, 2004.
14. E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, "QNoC: QoS architecture and design process for network on chip," Journal of Systems Architecture, vol. 50, no. 2, pp. 105-128, Feb. 2004.
15. A. Mello, L. Tedesco, N. Calazans, and F. Moraes, "Virtual channels in networks on chip: implementation and evaluation on hermes NoC," in Proceedings of the 18th annual symposium on Integrated circuits and system design, pp. 178-183, 2005.
16. T. Bjerregaard and J. Sparso, "Virtual channel designs for guaranteeing bandwidth in asynchronous network-on-chip," in Norchip Conference, 2004. Proceedings, pp. 269-272, 2004.
17. K. Goossens, J. Dielissen, and A. Radulescu, "AEthereal network on chip: concepts, architectures, and implementations," Design & Test of Computers, IEEE, vol. 22, no. 5, pp. 414-421, 2005.
18. M. Schoeberl, "A Time-Triggered Network-on-Chip," in Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on, pp. 377-382, 2007.