Quantitative analysis of the speed/accuracy trade-off in transaction level modeling

Transactions on Embedded Computing Systems

Volumn 8, Issue 1, 2008, Pages

  Schirner, Gunar ^a,b   Dömer, Rainer ^a,b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

System level design; System on chip; Transaction level modeling

Indexed keywords

ABSTRACT MODELS; ABSTRACTION LEVEL; ADVANCED HIGH PERFORMANCE BUS; APPROPRIATE METRICS; BUS ARCHITECTURE; COMMUNICATION PROTOCOLS; CONTROLLER AREA NETWORK; EMBEDDED PROCESSORS; FOUR-ORDER; HIGH SPEED SYSTEMS; LEVELS OF ABSTRACTION; MODEL ACCURACY; MOTOROLA; OFF-CHIP; ON CHIPS; QUANTITATIVE ANALYSIS; RAPID DESIGN; SERIAL BUS; SIMULATION SPEED; SYSTEM DESIGNERS; SYSTEM LEVEL DESIGN; SYSTEM-ON-CHIP; TEST SETUPS; TRANSACTION LEVEL MODELING;

ABSTRACTING; APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUSES; COMMERCE; COMMUNICATION; COMPUTER ARCHITECTURE; CONTROL SYSTEM SYNTHESIS; DESIGN; EMBEDDED SYSTEMS; NETWORK ARCHITECTURE; PARALLEL ARCHITECTURES; PROGRAMMABLE LOGIC CONTROLLERS; SPACE RESEARCH; SYSTEMS ANALYSIS;

SIMULATORS;

EID: 67549107026     PISSN: 15399087     EISSN: 15583465     Source Type: Journal    
DOI: 10.1145/1457246.1457250     Document Type: Article

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