A novel approach for network on chip emulation

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 2365-2368

  Genko, N ^a   Atienza, D ^b,d   De Micheli, G ^a   Benini, L ^c   Mendias, J M ^b   Hermida, R ^b   Catthoor, F ^d  

^a STANFORD UNIVERSITY   (United States)

^b UNIVERSIDAD COMPLUTENSE DE MADRID   (Spain)

^c UNIVERSITY OF BOLOGNA   (Italy)

^d IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

BUS-BASED; CURRENT SYSTEM; CYCLE ACCURATE; EMULATION FRAMEWORK; FOUR-ORDER; FUNCTIONAL VALIDATION; HDL SIMULATION; NETWORK ON CHIP; NETWORKS ON CHIPS; PARALLEL PROCESSING; SPEED-UP;

ELECTRIC NETWORK TOPOLOGY; MICROPROCESSOR CHIPS;

PARALLEL PROCESSING SYSTEMS;

EID: 33745775177     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465100     Document Type: Conference Paper

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