Source-level timing annotation for fast and accurate TLM computation model generation

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2010, Pages 235-240

  Lin, Kai Li ^a   Lo, Chen Kang ^a   Tsay, Ren Song ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ACCURATE ESTIMATION; ACCURATE TIMING; CACHE STRUCTURE; COMPUTATION MODEL; COMPUTATION MODULES; CYCLE ACCURATE; PROCESSOR ARCHITECTURES; SYSTEM LEVELS; SYSTEM MODELING AND SIMULATION; TIMING ANNOTATIONS; TIMING ESTIMATION; TRANSACTION LEVEL MODELING; TRANSACTION LEVEL MODELS;

COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; DISPENSERS; ESTIMATION;

TIME MEASUREMENT;

EID: 77951247076     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2010.5419890     Document Type: Conference Paper

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