Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 34, Issue 7, 2015, Pages 1082-1095

  Hills, Gage ^a   Zhang, Jie ^a   Shulaker, Max Marcel ^a   Wei, Hai ^a   Lee, Chi Shuen ^a   Balasingam, Arjun ^a   Wong, H S Philip ^a   Mitra, Subhasish ^a  

^a Stanford University   (United States)

Author keywords

Carbon Nanotube; Carbon Nanotube Variations; Delay Optimization; Design Technology Co optimization

Indexed keywords

CARBON NANOTUBE FIELD EFFECT TRANSISTORS; DESIGN; ENERGY EFFICIENCY; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUIT MANUFACTURE; YARN;

AD-HOC TECHNIQUES; BUILDING ENERGY; CIRCUIT DESIGNS; CO-OPTIMIZATION; DELAY OPTIMIZATION; PROCESSING PARAMETERS; SCALED TECHNOLOGIES; TRIAL AND ERROR;

CARBON NANOTUBES;

EID: 84933056024     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2015.2415492     Document Type: Article

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