Carbon nanotube circuit integration up to sub-20 nm channel lengths

ACS Nano

Volumn 8, Issue 4, 2014, Pages 3434-3443

  Shulaker, Max Marcel ^a   Van Rethy, Jelle ^b   Wu, Tony F ^a   Suriyasena Liyanage, Luckshitha ^a   Wei, Hai ^a   Li, Zuanyi ^a,c   Pop, Eric ^a   Gielen, Georges ^b   Wong, H S Philip ^a   Mitra, Subhasish ^a  

^a Stanford University   (United States)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c University of Illinois at Urbana Champaign   (United States)

Author keywords

carbon nanotube; CNFET; CNT; interface circuit; scaling; VLSI

Indexed keywords

CARBON NANOTUBES; DELAY CIRCUITS; ENERGY EFFICIENCY; FIELD EFFECT TRANSISTORS; LOGIC CIRCUITS; TECHNOLOGY;

CNFET; CNT; INTERFACE CIRCUITS; SCALING; VLSI;

VLSI CIRCUITS;

EID: 84899429472     PISSN: 19360851     EISSN: 1936086X     Source Type: Journal    
DOI: 10.1021/nn406301r     Document Type: Article

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