Monolithic 3D integration of logic and memory: Carbon nanotube FETs, resistive RAM, and silicon FETs

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2015-February, Issue February, 2015, Pages 27.4.1-27.4.4

  Shulaker, Max M ^a   Wu, Tony F ^a   Pal, Asish ^a   Zhao, Liang ^a   Nishi, Yoshio ^a   Saraswat, Krishna ^a   Wong, H S Philip ^a   Mitra, Subhasish ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CARBON NANOTUBES; ELECTRON DEVICES; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATION; METALS; MONOLITHIC INTEGRATED CIRCUITS; PROCESSING; RRAM; SILICON; THREE DIMENSIONAL INTEGRATED CIRCUITS;

3-D INTEGRATION; CARBON NANOTUBE FET; LOW PROCESSING TEMPERATURE; MEMORY ELEMENT; MEMORY LAYERS; RESISTIVE RANDOM ACCESS MEMORY (RRAM); STACKED LAYER; VERTICAL STACKING;

COMPUTER CIRCUITS;

EID: 84938251663     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2014.7047120     Document Type: Conference Paper

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