High performance CMOS variability in the 65nm regime and beyond

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2007, Pages 569-571

  Nassif, Sani ^a   Bernstein, Kerry ^a   Frank, David J ^a   Gattiker, Anne ^a   Haensch, Wilfried ^a   Ji, Brian L ^a   Nowak, Ed ^b   Pearson, Dale ^a   Rohrer, Norman J ^b  

^a IBM RESEARCH   (United States)

^b IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 48649091785     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2007.4419002     Document Type: Conference Paper

References (7)

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3. S. Nassif, J. Kozhaya, "Fast Power Grid Simulation," DAC 2000.
4. P. A. Stolk, et. al. "Modeling Statistical Dopant Fluctuations in MOS Transistors," ED, Sept. 1998.
5. E. B. Chang et. al. "Using a Statistical Metrology Framework to Identify Random and Systematic Sources of Intra-Die ILD Thickness Variation for CMP Processes" IEDM 1995.
6. K. Agarwal et. al. "A Test Structure for Characterizing Local Device Mismatches" VLSI 2006.
7. N. J. Rohrer et. al. "PowerPC 970 in 130nm and 90nm Technologies" JSSC 2004.