A reliability enhanced address mapping strategy for three-dimensional (3-D) NAND flash memory

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 22, Issue 11, 2014, Pages 2402-2410

  Wang, Yi ^a   Shao, Zili ^a   Chan, Henry C B ^a   Bathen, Luis Angel D ^b   Dutt, Nikil D ^b  

^a HONG KONG POLYTECHNIC UNIVERSITY   (Hong Kong)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

3 D integrated circuits; data storage systems; error correction codes; fault tolerance; flash memories; reliability

Indexed keywords

FLASH MEMORY; RELIABILITY;

3-D INTEGRATED CIRCUIT; ADDRESS MAPPINGS; DATA STORAGE SYSTEMS; ERROR CORRECTION CODES; NAND FLASH MEMORY; THREEDIMENSIONAL (3-D);

FAULT TOLERANCE;

EID: 84908299650     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2013.2288687     Document Type: Article

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