A critical examination of 3D stackable NAND flash memory architectures by simulation study of the scaling capability

2010 IEEE International Memory Workshop, IMW 2010

Volumn , Issue , 2010, Pages

  Hsiao, Yi Hsuan ^a   Lue, Hang Ting ^a   Hsu, Tzu Hsuan ^a   Hsieh, Kuang Yeu ^a   Lu, Chih Yuan ^a  

^a MACRONIX INTERNATIONAL CO LTD   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL CURRENTS; CHANNEL JUNCTIONS; CHANNEL THICKNESS; LAYER NUMBER; NAND FLASH; NAND FLASH MEMORY; READ CURRENT; SCALING CAPABILITY; SCALING LIMITATION; SIMULATION RESULT; SIMULATION STUDIES; TCAD SIMULATION; Z-DIRECTIONS;

THREE DIMENSIONAL;

FLASH MEMORY;

EID: 77957918328     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IMW.2010.5488390     Document Type: Conference Paper

References (14)

1. H. Tanaka, et al, VLSI Symposia, pp. 14-15, 2007.
2. R. Katsumata, et al, VLSI Symposia, pp. 136-137, 2009.
3. J. Jang, et al, VLSI Symposia, pp. 192-193, 2009.
4. J. Kim, et al, VLSI Symposia, pp. 186-187, 2009.
5. W. Kim, et al, VLSI Symposia, pp. 188-189, 2009.
6. H. T. Lue, et al, VLSI Symposia, pp. 140-141, 2008.
7. C. H. Lee, et al, VLSI Symposia, pp. 118-119, 2008.
8. H. T. Lue, et al, VLSI Symposia, pp. 224-225, 2009.
9. Y. H. Hsiao, et al, IMW, pp. 34-35, 2009.
10. T. H. Hsu, et al, IEEE T-ED, pp. 1235-1242, 2009.
11. E. K. Lai, et al, IEDM, pp. 41-44, 2006.
12. S. M. Jung, et al, IEDM, pp. 37-40, 2006.
13. H. T. Lue, et al, submitted to VLSI Symposia, 2010.
14. A. Hubert, et al, IEDM, pp. 637-640, 2009.