Vertical cell array using TCAT(terabit cell array transistor) technology for ultra high density NAND flash memory

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2009, Pages 192-193

  Jang, Jaehoon ^a   Kim, Han Soo ^a   Cho, Wonseok ^a   Cho, Hoosung ^a   Kim, Jinho ^a   Sun, Il Shim ^a   Jang, Younggoan ^a   Jeong, Jae Hun ^a   Son, Byoung Keun ^a   Dong, Woo Kim ^a   Kim, Kihyun ^a   Shim, Jae Joo ^a   Jin, Soo Lim ^a   Kim, Kyoung Hoon ^a   Su, Youn Yi ^a   Lim, Ju Young ^a   Chung, Dewill ^a   Moon, Hui Chang ^a   Hwang, Sungmin ^a   Lee, Jong Wook ^a   Son, Yong Hoon ^a   Chung, U In ^a   Lee, Won Seong ^a   more..

^a Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BIT COST; CELL ARRAY; ERASE OPERATION; GATE REPLACEMENT; METAL GATE; NAND FLASH; NAND FLASH MEMORY; TERABIT; ULTRAHIGH DENSITY;

NAND CIRCUITS; TECHNOLOGY;

FLASH MEMORY;

EID: 71049151625     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. H. Tanaka, et al, VLSI Symp. Tech. Dig., pp14-15, 2007
2. Chang Hyun Lee, et al, IEDM Tech. Dig., pp613-616, 2003
3. Y. Fukuzumi, et al., IEDM Tech. Dig., pp449-452, 2007