3D-FlashMap: A physical-location-aware block mapping strategy for 3D NAND flash memory

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2012, Pages 1307-1312

  Wang, Yi ^a   Bathen, Luis Angel D ^b   Shao, Zili ^a   Dutt, Nikil D ^b  

^a HONG KONG POLYTECHNIC UNIVERSITY   (Hong Kong)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT COST; BIT DENSITY; FLASH STORAGE; MAPPING STRATEGY; MULTIPLE LAYERS; NAND FLASH MEMORY; PHYSICAL ARCHITECTURE; PHYSICAL MAPPING; SPACE OVERHEAD; STORAGE CAPACITY;

COST REDUCTION; EXHIBITIONS; FLASH MEMORY; MAPPING; NAND CIRCUITS;

THREE DIMENSIONAL;

EID: 84862109503     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

1. E.-S. Choi, H.-S. Yoo, H.-S. Joo, G.-S. Cho, S.-K. Park, and S.-K. Lee, "A novel 3D cell array architecture for terra-bit NAND flash memory,"in 3rd IEEE International Memory Workshop, 2011, pp. 1-4.
2. H. Tanaka, M. Kido, K. Yahashi, M. Oomura, R. Katsumata, M. Kito, Y. Fukuzumi, M. Sato, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi, and A. Nitayama, "Bit cost scalable technology with punch and plug process for ultra high density flash memory," in VLSIT '07, 2007, pp. 14-15.
3. J. Kim, A. Hong, S. Kim, K.-S. Shin, E. Song, Y. Hwang, F. Xiu, K. Galatsis, C. Chui, R. Candler, S. Choi, J.-T. Moon, and K. Wang, "A stacked memory device on logic 3D technology for ultra-high-density data storage," Nanotechnology, vol. 22, no. 25, pp. 332-343, 2011.
4. L. M. Grupp, A. M. Caulfield, J. Coburn, S. Swanson, E. Yaakobi, P. H. Siegel, and J. K. Wolf, "Characterizing flash memory: anomalies, observations, and applications," in MICRO '09, 2009, pp. 24-33.
5. Y. Kang and E. L. Miller, "Adding aggressive error correction to a high-performance compressing flash file system," in EMSOFT '09, 2009, pp. 305-314.
6. P.-H. Hsu, Y.-H. Chang, P.-C. Huang, T.-W. Kuo, and D. H.-C. Du, "A version-based strategy for reliability enhancement of flash file systems,"in DAC '11, 2011, pp. 29-34.
7. T.-W. Kuo, Y.-H. Chang, P.-C. Huang, and C.-W. Chang, "Special issues in flash," in ICCAD '08, 2008, pp. 821-826.
8. Y. Wang, D. Liu, Z. Qin, and Z. Shao, "An endurance-enhanced flash translation layer via reuse for NAND flash memory storage systems,"in DATE '11, 2011, pp. 14-20.
9. R. Katsumata, M. Kito, Y. Fukuzumi, M. Kido, H. Tanaka, Y. Komori, M. Ishiduki, J. Matsunami, T. Fujiwara, Y. Nagata, L. Zhang, Y. Iwata, R. Kirisawa, H. Aochi, and A. Nitayama, "Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices," in VLSIT '09, 2009, pp. 136-137.
10. J. Jang, H.-S. Kim, W. Cho, H. Cho, J. Kim, S. I. Shim, Y. Jang, J.-H. Jeong, B.-K. Son, D. W. Kim, Kihyun, J.-J. Shim, J. S. Lim, K.-H. Kim, S. Y. Yi, J.-Y. Lim, D. Chung, H.-C. Moon, S. Hwang, J.-W. Lee, Y.-H. Son, U.-I. Chung, and W.-S. Lee, "Vertical cell array using TCAT (Terabit Cell Array Transistor) technology for ultra high density NAND flash memory," in VLSIT '09, 2009, pp. 192 -193.
11. J. Kim, A. Hong, S. M. Kim, E. Song, J. H. Park, J. Han, S. Choi, D. Jang, J. T. Moon, and K. Wang, "Novel Vertical-Stacked-Array-Transistor (VSAT) for ultra-high-density and cost-effective NAND flash memory devices and SSD (Solid State Drive)," in VLSIT '09, 2009, pp. 186-187.
12. W. Kim, S. Choi, J. Sung, T. Lee, C. Park, H. Ko, J. Jung, I. Yoo, and Y. Park, "Multi-layered vertical gate NAND flash overcoming stacking limit for terabit density storage," in VLSIT '09, 2009, pp. 188-189.
13. Z. Qin, Y. Wang, D. Liu, Z. Shao, and Y. Guan, "MNFTL: An efficient flash translation layer for MLC NAND flash memory storage systems,"in DAC '11, 2011, pp. 17-22.
14. "Memory Technology Device (MTD) Subsystem for Linux,"http:// www.linux-mtd.infradead.org/, 2011.
15. "DiskMon for Windows," http://technet.microsoft.com/enus/ sysinternals/ bb896646.aspx.