Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2009, Pages 136-137

  Katsumata, Ryota ^a   Kito, Masaru ^a   Fukuzumi, Yoshiaki ^a   Kido, Masaru ^a   Tanaka, Hiroyasu ^a   Komori, Yosuke ^a   Ishiduki, Megumi ^a   Matsunami, Junya ^a   Fujiwara, Tomoko ^a   Nagata, Yuzo ^a   Zhang, Li ^a   Iwata, Yoshihisa ^a   Kirisawa, Ryouhei ^a   Aochi, Hideaki ^a   Nitayama, Akihiro ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIT CELL; BIT COST; CELL OPERATION; CONTROLLED DIFFUSION; CURVATURE EFFECT; FLASH TECHNOLOGY; FOWLER-NORDHEIM TUNNELING; LOW RESISTANCE; LOW THERMAL BUDGET; MEMORY FILM; MULTI-LEVEL; PROGRAM AND ERASE; SMALL PIPES; STACKED LAYER; STORAGE DEVICES; STRAIGHT-SHAPE; TEST CHIPS; ULTRAHIGH DENSITY;

PIPE; TECHNOLOGY;

FLASH MEMORY;

EID: 71049162177     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. H. Tanaka et al., Symp. on VLSI Tech. Dig., pp14-15, 2007.
2. Y. Fukuzumi et al., IEDM Tech. Dig., pp449-452, 2007.
3. H. Aochi et al., Ext. Abs. SSDM, pp820-821, 2008.
4. Y. Komori et al., IEDM Tech. Dig., pp851-854, 2008.
5. S. Lai, IEDM Tech. Dig., pp11-16, 2008.
6. L. Zhang et al, IEEE Electron Device Letter, Vol.29, Issue 7 pp.799-801, 2008.