-
1
-
-
70350706851
-
Special issues in flash
-
Nov
-
T.-W. Kuo, Y.-H. Chang, P.-C. Huang, and C.-W. Chang, "Special issues in flash," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, Nov. 2008, pp. 821-826.
-
(2008)
Proc IEEE/ACM Int. Conf. Comput.-Aided Design
, pp. 821-826
-
-
Kuo, T.-W.1
Chang, Y.-H.2
Huang, P.-C.3
Chang, C.-W.4
-
3
-
-
85001155071
-
Efficient management for large-scale flashmemory storage systems with resource conservation
-
C. Li-Pin and K. Tei-Wei, "Efficient management for large-scale flashmemory storage systems with resource conservation," ACM Trans. Storage, vol. 1, no. 4, pp. 381-418, 2005.
-
(2005)
ACM Trans. Storage
, vol.1
, Issue.4
, pp. 381-418
-
-
Li-Pin, C.1
Tei-Wei, K.2
-
4
-
-
84991957861
-
Design tradeoffs for SSD performance
-
N. Agrawal, V. Prabhakaran, T. Wobber, J. D. Davis, M. Manasse, and R. Panigrahy, "Design tradeoffs for SSD performance," in Proc. USENIX Annu. Tech. Conf., 2008, pp. 57-70.
-
(2008)
Proc. USENIX Annu. Tech. Conf
, pp. 57-70
-
-
Agrawal, N.1
Prabhakaran, V.2
Wobber, T.3
Davis, J.D.4
Manasse, M.5
Panigrahy, R.6
-
5
-
-
84884322202
-
An adaptive striping architecture for flash memory storage systems of embedded systems
-
Nov
-
L.-P. Chang and T.-W. Kuo, "An adaptive striping architecture for flash memory storage systems of embedded systems," in Proc. 8th IEEE Real-Time Embed. Technol. Appl. Symp., Nov. 2002, pp. 187-196.
-
(2002)
Proc. 8th IEEE Real-Time Embed. Technol. Appl. Symp.
, pp. 187-196
-
-
Chang, L.-P.1
Kuo, T.-W.2
-
6
-
-
79952919587
-
Register allocation for write activity minimization on non-volatile main memory
-
Jan
-
Y. Huang, T. Liu, and C. Xue, "Register allocation for write activity minimization on non-volatile main memory," in Proc. 16th Asia South Pacific Design Autom. Conf., Jan. 2011, pp. 129-134.
-
(2011)
Proc. 16th Asia South Pacific Design Autom. Conf.
, pp. 129-134
-
-
Huang, Y.1
Liu, T.2
Xue, C.3
-
7
-
-
84055224110
-
Register allocation for write activity minimization on non-volatile main memory for embedded systems
-
Y. Huang, T. Liu, and C. J. Xue, "Register allocation for write activity minimization on non-volatile main memory for embedded systems," J. Syst. Arch., vol. 58, no. 1, pp. 13-23, 2012.
-
(2012)
J. Syst. Arch
, vol.58
, Issue.1
, pp. 13-23
-
-
Huang, Y.1
Liu, T.2
Xue, C.J.3
-
8
-
-
77954496810
-
Write activity reduction on flash main memory via smart victim cache
-
L. Shi, C. J. Xue, J. Hu, W.-C. Tseng, X. Zhou, and E. H.-M. Sha, "Write activity reduction on flash main memory via smart victim cache," in Proc. 20th Symp. Great Lakes Very Large Scale Integr. Syst., 2010, pp. 91-94.
-
(2010)
Proc. 20th Symp. Great Lakes Very Large Scale Integr. Syst
, pp. 91-94
-
-
Shi, L.1
Xue, C.J.2
Hu, J.3
Tseng, W.-C.4
Zhou, X.5
Sha, E.H.-M.6
-
9
-
-
33747027155
-
FAB: Flash-aware buffer management policy for portable media players
-
DOI 10.1109/TCE.2006.1649669
-
H. Jo, J.-U. Kang, S.-Y. Park, J.-S. Kim, and J. Lee, "FAB: Flash-aware buffer management policy for portable media players," IEEE Trans. Consumer Electron., vol. 52, no. 2, pp. 485-493, May 2006. (Pubitemid 44203122)
-
(2006)
IEEE Transactions on Consumer Electronics
, vol.52
, Issue.2
, pp. 485-493
-
-
Jo, H.1
Kang, J.-U.2
Park, S.-Y.3
Kim, J.-S.4
Lee, J.5
-
10
-
-
85075012374
-
BPLRU: A buffer management scheme for improving random writes in flash storage
-
H. Kim and S. Ahn, "BPLRU: A buffer management scheme for improving random writes in flash storage," in Proc. 6th USENIX Conf. File Storage Technol., 2008, pp. 1-14.
-
(2008)
Proc. 6th USENIX Conf. File Storage Technol
, pp. 1-14
-
-
Kim, H.1
Ahn, S.2
-
11
-
-
34547194263
-
CFLRU: A replacement algorithm for flash memory
-
DOI 10.1145/1176760.1176789, CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems
-
S.-Y. Park, D. Jung, J.-U. Kang, J.-S. Kim, and J. Lee, "CFLRU: A replacement algorithm for flash memory," in Proc. Int. Conf. Compil., Arch. Synth. Embed. Syst., 2006, pp. 234-241. (Pubitemid 47113111)
-
(2006)
CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems
, pp. 234-241
-
-
Park, S.-Y.1
Jung, D.2
Kang, J.-U.3
Kim, J.-S.4
Lee, J.5
-
12
-
-
80455129057
-
EXLRU: A unified write buffer cache management for flash memory
-
L. Shi, J. Li, C. J. Xue, C. Yang, and X. Zhou, "EXLRU: A unified write buffer cache management for flash memory," in Proc. ACM Int. Conf. Embed. Softw., 2011, pp. 339-348.
-
(2011)
Proc. ACM Int. Conf. Embed. Softw
, pp. 339-348
-
-
Shi, L.1
Li, J.2
Xue, C.J.3
Yang, C.4
Zhou, X.5
-
13
-
-
0036564365
-
A space-efficient flash translation layer for compactflash systems
-
DOI 10.1109/TCE.2002.1010143
-
J. Kim, J. M. Kim, S. Noh, S. L. Min, and Y. Cho, "A space-efficient flash translation layer for compactflash systems," IEEE Trans. Consumer Electron., vol. 48, no. 2, pp. 366-375, May 2002. (Pubitemid 34798899)
-
(2002)
IEEE Transactions on Consumer Electronics
, vol.48
, Issue.2
, pp. 366-375
-
-
Kim, J.1
Kim, J.M.2
Noh, S.H.3
Min, S.L.4
Cho, Y.5
-
14
-
-
85025155936
-
A log buffer-based flash translation layer using fully-associative sector translation
-
S.-W. Lee, D.-J. Park, T.-S. Chung, D.-H. Lee, S. Park, and H.-J. Song, "A log buffer-based flash translation layer using fully-associative sector translation," ACM Trans. Embed. Comput. Syst., vol. 6, no. 3, pp. 1-18, 2007.
-
(2007)
ACM Trans. Embed. Comput. Syst
, vol.6
, Issue.3
, pp. 1-18
-
-
Lee, S.-W.1
Park, D.-J.2
Chung, T.-S.3
Lee, D.-H.4
Park, S.5
Song, H.-J.6
-
15
-
-
66049112804
-
Performance trade-offs in using NVRAM write buffer for flash memory-based storage devices
-
Jun
-
S. Kang, S. Park, H. Jung, H. Shim, and J. Cha, "Performance trade-offs in using NVRAM write buffer for flash memory-based storage devices," IEEE Trans. Comput., vol. 58, no. 6, pp. 744-758, Jun. 2009.
-
(2009)
IEEE Trans. Comput
, vol.58
, Issue.6
, pp. 744-758
-
-
Kang, S.1
Park, S.2
Jung, H.3
Shim, H.4
Cha, J.5
-
16
-
-
54349108939
-
Recently-evicted-first buffer replacement policy for flash storage devices
-
Aug
-
D. Seo and D. Shin, "Recently-evicted-first buffer replacement policy for flash storage devices," IEEE Trans. Consumer Electron., vol. 54, no. 3, pp. 1228-1235, Aug. 2008.
-
(2008)
IEEE Trans. Consumer Electron
, vol.54
, Issue.3
, pp. 1228-1235
-
-
Seo, D.1
Shin, D.2
-
17
-
-
72049089888
-
A buffer replacement algorithm exploiting multi-chip parallelism in solid state disks
-
J. Seol, H. Shim, J. Kim, and S. Maeng, "A buffer replacement algorithm exploiting multi-chip parallelism in solid state disks," in Proc. Int. Conf. Compil., Arch., Synth. Embed. Syst., 2009, pp. 137-146.
-
(2009)
Proc. Int. Conf. Compil., Arch., Synth. Embed. Syst
, pp. 137-146
-
-
Seol, J.1
Shim, H.2
Kim, J.3
Maeng, S.4
-
18
-
-
77957717506
-
Write amplification analysis in flash-based solid state drives
-
X.-Y. Hu, E. Eleftheriou, R. Haas, I. Iliadis, and R. Pletka, "Write amplification analysis in flash-based solid state drives," in Proc. SYSTOR: Israeli Experim. Syst. Conf., 2009, pp. 1-9.
-
(2009)
Proc. SYSTOR: Israeli Experim. Syst. Conf
, pp. 1-9
-
-
Hu, X.-Y.1
Eleftheriou, E.2
Haas, R.3
Iliadis, I.4
Pletka, R.5
-
19
-
-
54349109403
-
LRU-WSR: Integration of LRU and writes sequence reordering for flash memory
-
Aug
-
H. Jung, H. Shim, S. Park, S. Kang, and J. Cha, "LRU-WSR: Integration of LRU and writes sequence reordering for flash memory," IEEE Trans. Consumer Electron., vol. 54, no. 3, pp. 1215-1223, Aug. 2008.
-
(2008)
IEEE Trans. Consumer Electron
, vol.54
, Issue.3
, pp. 1215-1223
-
-
Jung, H.1
Shim, H.2
Park, S.3
Kang, S.4
Cha, J.5
-
20
-
-
70449671106
-
CFDC: A flash-aware replacement policy for database buffer management
-
Y. Ou, T. Härder, and P. Jin, "CFDC: A flash-aware replacement policy for database buffer management," in Proc. 5th Int. Workshop Data Manage. New Hardw., 2009, pp. 15-20.
-
(2009)
Proc. 5th Int. Workshop Data Manage. New Hardw
, pp. 15-20
-
-
Ou, Y.1
Härder, T.2
Jin, P.3
-
21
-
-
79957613959
-
Cooperating write buffer cache and virtual memory management for flash memory based systems
-
Apr
-
L. Shi, C. J. Xue, and X. Zhou, "Cooperating write buffer cache and virtual memory management for flash memory based systems," in Proc. 17th IEEE Real-Time Embed. Technol. Appl. Symp., Apr. 2011, pp. 147-156.
-
(2011)
Proc. 17th IEEE Real-Time Embed. Technol. Appl. Symp.
, pp. 147-156
-
-
Shi, L.1
Xue, C.J.2
Zhou, X.3
-
22
-
-
70350284593
-
CCF-LRU: A new buffer replacement algorithm for flash memory
-
Aug
-
Z. Li, P. Jin, X. Su, K. Cui, and L. Yue, "CCF-LRU: A new buffer replacement algorithm for flash memory," IEEE Trans. Consumer Electron., vol. 55, no. 3, pp. 1351-1359, Aug. 2009.
-
(2009)
IEEE Trans. Consumer Electron
, vol.55
, Issue.3
, pp. 1351-1359
-
-
Li, Z.1
Jin, P.2
Su, X.3
Cui, K.4
Yue, L.5
-
23
-
-
79959930829
-
Operation-aware buffer management in flash-based systems
-
Y. Lv, B. Cui, B. He, and X. Chen, "Operation-aware buffer management in flash-based systems," in Proc. SIGMOD Int. Conf. Manage. Data, 2011, pp. 13-24.
-
(2011)
Proc. SIGMOD Int. Conf. Manage. Data
, pp. 13-24
-
-
Lv, Y.1
Cui, B.2
He, B.3
Chen, X.4
-
24
-
-
83755163091
-
Exploiting set-level write non-uniformity for energy-efficient NVM-based hybrid cache
-
Oct
-
J. Li, L. Shi, C. Xue, C. Yang, and Y. Xu, "Exploiting set-level write non-uniformity for energy-efficient NVM-based hybrid cache," in Proc. 9th IEEE Symp. Embed. Syst. Real-Time Multimedia, Oct. 2011, pp. 19-28.
-
(2011)
Proc. 9th IEEE Symp. Embed. Syst. Real-Time Multimedia
, pp. 19-28
-
-
Li, J.1
Shi, L.2
Xue, C.3
Yang, C.4
Xu, Y.5
-
25
-
-
83755219446
-
STT-RAM based energy-efficiency hybrid cache for CMPs
-
Oct
-
J. Li, C. Xue, and Y. Xu, "STT-RAM based energy-efficiency hybrid cache for CMPs," in Proc. IEEE/IFIP 19th Int. Conf. Very Large Scale Integr. Syst. Syst.-Chip, Oct. 2011, pp. 31-36.
-
(2011)
Proc IEEE/IFIP 19th Int. Conf. Very Large Scale Integr. Syst. Syst.-Chip
, pp. 31-36
-
-
Li, J.1
Xue, C.2
Xu, Y.3
-
26
-
-
81355136046
-
Emerging non-volatile memories: Opportunities and challenges
-
Oct
-
C. J. Xue, Y. Zhang, Y. Chen, G. Sun, J. J. Yang, and H. Li, "Emerging non-volatile memories: Opportunities and challenges," in Proc. IEEE/ACM/IFIP Int. Conf. Hardw./Softw. Codesign Syst. Synth., Oct. 2011, pp. 325-334.
-
(2011)
Proc. IEEE/ACM/IFIP Int. Conf. Hardw./Softw. Codesign Syst. Synth.
, pp. 325-334
-
-
Xue, C.J.1
Zhang, Y.2
Chen, Y.3
Sun, G.4
Yang, J.J.5
Li, H.6
-
27
-
-
42149105894
-
Write strategies for 2 and 4-bit multi-level phase-change memory
-
Dec
-
T. Nirschl, J. B. Phipp, T. D. Happ, G. W. Burr, B. Rajendran, M.-H. Lee, A. Schrott, M. Yang, M. Breitwisch, C.-F. Chen, E. Joseph, M. Lamorey, R. Cheek, S.-H. Chen, S. Zaidi, S. Raoux, Y. C. Chen, Y. Zhu, R. Bergmann, H.-L. Lung, and C. Lam, "Write strategies for 2 and 4-bit multi-level phase-change memory," in Proc. IEEE IEDM, Dec. 2007, pp. 461-464.
-
(2007)
Proc. IEEE IEDM
, pp. 461-464
-
-
Nirschl, T.1
Phipp, J.B.2
Happ, T.D.3
Burr, G.W.4
Rajendran, B.5
Lee, M.-H.6
Schrott, A.7
Yang, M.8
Breitwisch, M.9
Chen, C.-F.10
Joseph, E.11
Lamorey, M.12
Cheek, R.13
Chen, S.-H.14
Zaidi, S.15
Raoux, S.16
Chen, Y.C.17
Zhu, Y.18
Bergmann, R.19
Lung, H.-L.20
Lam, C.21
more..
-
28
-
-
0018480749
-
Ubiquitous B-tree
-
D. Comer, "Ubiquitous B-tree," J. ACM Comput. Surveys, vol. 11, no. 2, pp. 121-137, 1979.
-
(1979)
J. ACM. Comput. Surveys
, vol.11
, Issue.2
, pp. 121-137
-
-
Comer, D.1
-
29
-
-
84875635456
-
-
Samsung Electronics Company, Ltd., Seoul, South Korea Sep
-
Ikfguxm 1g 8 bit NAND Flash Memory Data Sheet, Samsung Electronics Company, Ltd., Seoul, South Korea, Sep. 2006.
-
(2006)
Ikfguxm 1g 8 Bit NAND Flash Memory Data Sheet
-
-
-
31
-
-
48349126780
-
Energy-aware flash memory management in virtual memory system
-
Aug
-
H.-L. Li, C.-L. Yang, and H.-W. Tseng, "Energy-aware flash memory management in virtual memory system," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 8, pp. 952-964, Aug. 2008.
-
(2008)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst
, vol.16
, Issue.8
, pp. 952-964
-
-
Li, H.-L.1
Yang, C.-L.2
Tseng, H.-W.3
-
32
-
-
67650783129
-
DFTL: A flash translation layer employing demand-based selective caching of page-level address mappings
-
A. Gupta, Y. Kim, and B. Urgaonkar, "DFTL: A flash translation layer employing demand-based selective caching of page-level address mappings," in Proc. 14th Int. Conf. Arch. Support Program. Lang. Operat. Syst., 2009, pp. 229-240.
-
(2009)
Proc. 14th Int. Conf. Arch. Support Program. Lang. Operat. Syst
, pp. 229-240
-
-
Gupta, A.1
Kim, Y.2
Urgaonkar, B.3
-
33
-
-
80052667106
-
MNFTL: An efficient flash translation layer for MLC NAND flash memory storage systems
-
Z. Qin, Y. Wang, D. Liu, Z. Shao, and Y. Guan, "MNFTL: An efficient flash translation layer for MLC NAND flash memory storage systems," in Proc. 48th Design Autom. Conf., 2011, pp. 17-22.
-
(2011)
Proc. 48th Design Autom. Conf
, pp. 17-22
-
-
Qin, Z.1
Wang, Y.2
Liu, D.3
Shao, Z.4
Guan, Y.5
-
34
-
-
79957578221
-
An endurance-enhanced flash translation layer via reuse for NAND flash memory storage systems
-
Mar
-
Y. Wang, D. Liu, Z. Qin, and Z. Shao, "An endurance-enhanced flash translation layer via reuse for NAND flash memory storage systems," in Proc. Design, Autom. Test Eur. Conf. Exhibit., Mar. 2011, pp. 1-6.
-
(2011)
Proc. Design, Autom. Test Eur. Conf. Exhibit.
, pp. 1-6
-
-
Wang, Y.1
Liu, D.2
Qin, Z.3
Shao, Z.4
-
35
-
-
77954531367
-
RNFTL: A reuse-aware NAND flash translation layer for flash memory
-
Y. Wang, D. Liu, M. Wang, Z. Qin, Z. Shao, and Y. Guan, "RNFTL: A reuse-aware NAND flash translation layer for flash memory," in Proc. ACM SIGPLAN/SIGBED Conf. Lang., Compil., Tools Embed. Syst., 2010, pp. 1-10.
-
(2010)
Proc ACM SIGPLAN/SIGBED Conf. Lang., Compil., Tools Embed. Syst
, pp. 1-10
-
-
Wang, Y.1
Liu, D.2
Wang, M.3
Qin, Z.4
Shao, Z.5
Guan, Y.6
-
36
-
-
38849194056
-
An adaptive two-level management for the flash translation layer in embedded systems
-
Nov
-
C.-H. Wu and T.-W. Kuo, "An adaptive two-level management for the flash translation layer in embedded systems," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, Nov. 2006, pp. 601-606.
-
(2006)
Proc IEEE/ACM Int. Conf. Comput.-Aided Design
, pp. 601-606
-
-
Wu, C.-H.1
Kuo, T.-W.2
|