-
1
-
-
0028752012
-
A 0.67um2 Self-Aligned Shallow Trench Isolation Cell(SA-STI CELL) for 3V-only 256Mbit NAND EEPROMs
-
S. Aritome, et al., "A 0.67um2 Self-Aligned Shallow Trench Isolation Cell(SA-STI CELL) for 3V-only 256Mbit NAND EEPROMs", IEEE IEDM Technical Digest, pp. 61-64, 1994.
-
(1994)
IEEE IEDM Technical Digest
, pp. 61-64
-
-
Aritome, S.1
-
2
-
-
0034453383
-
Advanced Flash Memory Technology and Trends for File Storage Application
-
S. Aritome, "Advanced Flash Memory Technology and Trends for File Storage Application", IEEE IEDM Technical Digest, pp. 763-766, 2000.
-
(2000)
IEEE IEDM Technical Digest
, pp. 763-766
-
-
Aritome, S.1
-
3
-
-
36448932248
-
Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory
-
H. Tanaka, et al., "Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory", VLSI Symposium Tech. Dig., 2007, pp. 14-15.
-
VLSI Symposium Tech. Dig., 2007
, pp. 14-15
-
-
Tanaka, H.1
-
4
-
-
50249134336
-
Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory
-
Yoshiaki Fukuzumi, et al., "Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory", IEEE IEDM Technical Digest, pp. 449-452, 2007.
-
(2007)
IEEE IEDM Technical Digest
, pp. 449-452
-
-
Fukuzumi, Y.1
-
5
-
-
64549122322
-
Disturbless Flash Memory due to High Boost Efficiency on BiCS Structure and Optimal Memory Film Stack for Ultra High Density Storage Device
-
Yosuke Komori, et al., "Disturbless Flash Memory due to High Boost Efficiency on BiCS Structure and Optimal Memory Film Stack for Ultra High Density Storage Device", IEEE IEDM Technical Digest, pp. 851-854, 2008.
-
(2008)
IEEE IEDM Technical Digest
, pp. 851-854
-
-
Komori, Y.1
-
6
-
-
71049162177
-
Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices
-
Ryota. Katsumata, et al., "Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices", VLSI Symposium Tech. Dig., 2009, pp. 136-137.
-
VLSI Symposium Tech. Dig., 2009
, pp. 136-137
-
-
Katsumata, R.1
-
7
-
-
70449382442
-
Multi-stacked 1G cell/layer Pipe-shaped BiCS Flash Memory
-
Takashi Maeda, et al., "Multi-stacked 1G cell/layer Pipe-shaped BiCS Flash Memory", VLSI Symposium Tech. Dig., 2009, pp. 22-23.
-
VLSI Symposium Tech. Dig., 2009
, pp. 22-23
-
-
Maeda, T.1
-
8
-
-
77952413372
-
Optimal Device Structure for Pipe-shaped BiCS Flash Memory for Ultra High Density Storage Device with Excellent Performance and Reliability
-
Megumi Ishiduki, et al., "Optimal Device Structure for Pipe-shaped BiCS Flash Memory for Ultra High Density Storage Device with Excellent Performance and Reliability", IEEE IEDM Technical Digest, pp. 625-628, 2009.
-
(2009)
IEEE IEDM Technical Digest
, pp. 625-628
-
-
Ishiduki, M.1
-
9
-
-
71049154997
-
Multi-Layered Vertical Gate NAND Flash Overcoming Stacking Limit for Terabit Density Storage
-
WonJoo Kim, et al., "Multi-Layered Vertical Gate NAND Flash Overcoming Stacking Limit for Terabit Density Storage", VLSI Symposium Tech. Dig., 2009, pp. 188-189.
-
VLSI Symposium Tech. Dig., 2009
, pp. 188-189
-
-
Kim, W.1
-
10
-
-
71049151625
-
Vertical Cell Array using TCAT(Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory
-
JaeHoon Jang, et al., "Vertical Cell Array using TCAT(Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory", VLSI Symposium Tech. Dig., 2009, pp. 192-193.
-
VLSI Symposium Tech. Dig., 2009
, pp. 192-193
-
-
Jang, J.1
-
11
-
-
77957903010
-
The 3-dimensional vertical FG NAND flash memory cell arrays with the novel electrical S/D technique using the extended sidewall control gate (ESCG)
-
MoonSik Seo, SungKye Park, and Tetsuo Endoh, "The 3-dimensional vertical FG NAND flash memory cell arrays with the novel electrical S/D technique using the extended sidewall control gate (ESCG)", IMW, 2010, pp. 146-149.
-
IMW, 2010
, pp. 146-149
-
-
Seo, M.1
Park, S.2
Endoh, T.3
-
12
-
-
34548754508
-
Effects of Lateral Charge Spreading on the Reliability of TANOS(TaN/AlO/SiN/Oxide/Si) NAND Flash Memory
-
ChangSeok Kang, et al., "Effects of Lateral Charge Spreading on the Reliability of TANOS(TaN/AlO/SiN/Oxide/Si) NAND Flash Memory", IRPS, 2007, pp. 167-169.
-
IRPS, 2007
, pp. 167-169
-
-
Kang, C.1
|