3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2012, Pages 1185-1190

  Chen, Yibo ^a   Sun, Guangyu ^b   Zou, Qiaosha ^c   Xie, Yuan ^c  

^a SYNOPSYS INC   (United States)

^b PEKING UNIVERSITY   (China)

^c PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D ICS; 3D IC DESIGN; BEHAVIORAL SYNTHESIS; DESIGN ABSTRACTIONS; FLOORPLANS; HIGH LEVEL SYNTHESIS; LAYER ASSIGNMENT; MULTIPLE LAYERS; NANOMETER CMOS; PEAK TEMPERATURES; PHYSICAL INFORMATION; PLANNING PROCESS; SYSTEM LEVELS; THREE DIMENSIONAL INTEGRATED CIRCUITS; THREE DIMENSIONAL INTEGRATION; THREE-DIMENSIONAL (3D) CIRCUITS; TIMING YIELD;

DATA FLOW ANALYSIS; DESIGN; EXHIBITIONS; INTEGRATED CIRCUITS;

THREE DIMENSIONAL;

EID: 84862113176     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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