Control gate length, spacing and stacked layer number design for 3D-stackable NAND flash memory

2012 4th IEEE International Memory Workshop, IMW 2012

Volumn , Issue , 2012, Pages

  Yanagihara, Yuki ^a   Miyaji, Kousuke ^a   Takeuchi, Ken ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

3D device simulation; 3D stackable NAND flash memory; component; control gate design; number of stacked layers; scaling

Indexed keywords

3D DEVICE SIMULATION; COMPONENT; CONTROL GATES; NAND FLASH MEMORY; SCALING; STACKED LAYER;

DESIGN; FLASH MEMORY; NAND CIRCUITS; THREE DIMENSIONAL;

THREE DIMENSIONAL COMPUTER GRAPHICS;

EID: 84864141002     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IMW.2012.6213656     Document Type: Conference Paper

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