A highly scalable vertical gate (VG) 3D NAND flash with robust program disturb immunity using a novel PN diode decoding structure

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2011, Pages 68-69

  Hung, Chun Hsiung ^a   Lue, Hang Ting ^c   Chang, Kuo Pin ^c   Chen, Chih Ping ^c   Hsiao, Yi Hsuan ^c   Chen, Shih Hung ^c   Shih, Yen Hao ^c   Hsieh, Kuang Yeu ^c   Yang, Mars ^b   Lee, James ^b   Wang, Szu Yu ^b   Yang, Tahone ^b   Chen, Kuang Chao ^b   Lu, Chih Yuan ^c  

^a Emerging Central Lab   (Taiwan)

^b MACRONIX INTERNATIONAL CO LTD   (Taiwan)

^c NONE

Author keywords

[No Author keywords available]

Indexed keywords

CELL STRUCTURE; CHANNEL POTENTIAL; DECODING METHODS; NAND FLASH; P-N DIODE; PROGRAMMING PULSE; SELF-ALIGNED;

DECODING; DIODES;

THREE DIMENSIONAL;

EID: 80052667352     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. R. Katsumata, et al, VLSI Symposia, pp. 136-137, 2009.
2. W. Kim, et al, VLSI Symposia, pp. 188-189, 2009.
3. H. T. Lue, et al, VLSI Symposia, pp. 131-132, 2010.
4. ITRS table for NAND Flash.
5. K. Takeuchi, VLSI Symposia, pp. 234-235, 1998.