-
1
-
-
36448932248
-
Bit cost scalable technology with punch and plug process for ultra high density flash memory
-
H. Tanaka et. al., "Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory," IEEE Symposium on VLSI Technology, pp.14-15, 2007.
-
(2007)
IEEE Symposium on VLSI Technology
, pp. 14-15
-
-
Tanaka, H.1
-
2
-
-
71049151625
-
Vertical cell array using TCAT(terabit cell array transistor) technology for ultra high density NAND flash memory
-
J. Jang et. al., "Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory," IEEE symposium on VLSI technology, pp. 192-193, 2009.
-
(2009)
IEEE Symposium on VLSI Technology
, pp. 192-193
-
-
Jang, J.1
-
3
-
-
79951846898
-
Novel 3-dimensional dual control-gate with surrounding floating-gate (DC-SF) NAND flash cell for 1Tb file storage application
-
S. Whang et. al., "Novel 3-dimensional dual control-gate with surrounding floating-gate (DC-SF) NAND flash cell for 1Tb file storage application," IEEE international electron devices meeting, pp. 668-671, 2010.
-
(2010)
IEEE International Electron Devices Meeting
, pp. 668-671
-
-
Whang, S.1
-
4
-
-
71049154997
-
Multi-layered vertical gate NAND flash overcoming stacking limit for terabit density storage
-
W. Kim et. al., "Multi-Layered Vertical Gate NAND Flash Overcoming Stacking Limit for Terabit Density Storage," IEEE Symposium on VLSI Technology, pp.188-189, 2009.
-
(2009)
IEEE Symposium on VLSI Technology
, pp. 188-189
-
-
Kim, W.1
-
5
-
-
77957918328
-
A critical examination of 3D stackable NAND flash memory architectures by simulation study of the scaling capability
-
Y. Hsiao et. al., "A Critical Examination of 3D Stackable NAND Flash Memory Architectures by Simulation Study of the Scaling Capability," IEEE International Memory Workshop, pp.142-145, 2010.
-
(2010)
IEEE International Memory Workshop
, pp. 142-145
-
-
Hsiao, Y.1
-
6
-
-
70449382442
-
Multi-stacked 1G cell/layer pipe-shaped BiCS flash memory
-
T. Maeda et. al., "Multi-stacked 1G cell/layer Pipe-shaped BiCS Flash Memory," IEEE Symposium on VLSI Circuits, pp.22-23, 2009.
-
(2009)
IEEE Symposium on VLSI Circuits
, pp. 22-23
-
-
Maeda, T.1
-
7
-
-
77957924169
-
Understanding the impact of metal gate on TANOS performance and retention
-
G. Van den bosch et. al., "Understanding the impact of metal gate on TANOS performance and retention," IEEE International Memory Workshop, pp.110-113, 2010.
-
(2010)
IEEE International Memory Workshop
, pp. 110-113
-
-
Van Den Bosch, G.1
-
8
-
-
48649091137
-
Modeling and characterization of program/erasure speed and retention of TiN-gate MANOS cells for NAND flash memory
-
E. Choi et. al., "Modeling and characterization of program/erasure speed and retention of TiN-gate MANOS cells for NAND flash memory," IEEE non-volitile semiconductor memory workshop, pp. 83-84, 2007.
-
(2007)
IEEE Non-volitile Semiconductor Memory Workshop
, pp. 83-84
-
-
Choi, E.1
-
9
-
-
70349986906
-
Chip level reliability of MANOS cells under operation conditions
-
E. Choi et. al., "Chip level reliability of MANOS cells under operation conditions," IEEE international memory workshop, pp. 92-93, 2009.
-
(2009)
IEEE International Memory Workshop
, pp. 92-93
-
-
Choi, E.1
|