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Volumn 48, Issue 5, 2013, Pages 1302-1314

A logic-compatible embedded flash memory for zero-standby power system-on-chips featuring a multi-story high voltage switch and a selective refresh scheme

Author keywords

Embedded flash memory; Embedded nonvolatile memory; Multi story high voltage switch; Selective WL refresh; Zero standby power system on chip

Indexed keywords

EMBEDDED FLASH MEMORY; HIGH VOLTAGE SWITCHES; NON-VOLATILE MEMORY; SELECTIVE WL REFRESH; SYSTEM ON CHIPS;

EID: 84892955163     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2013.2247691     Document Type: Article
Times cited : (34)

References (41)
  • 1
    • 63449098455 scopus 로고    scopus 로고
    • A low-voltage processor for sensing applications with picowatt standby mode
    • Apr.
    • S. Hanson et al., "A low-voltage processor for sensing applications with picowatt standby mode," IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1145-1155, Apr. 2009.
    • (2009) IEEE J. Solid-State Circuits , vol.44 , Issue.4 , pp. 1145-1155
    • Hanson, S.1
  • 7
    • 0033712805 scopus 로고    scopus 로고
    • A 60 ns access 32 kByte 3-transistor flash for low power embedded applications
    • T. Ikehashi et al., "A 60 ns access 32 kByte 3-transistor flash for low power embedded applications," in IEEE Symp. VLSI Circuits Dig., 2000, pp. 162-165.
    • IEEE Symp. VLSI Circuits Dig., 2000 , pp. 162-165
    • Ikehashi, T.1
  • 10
    • 70350000396 scopus 로고    scopus 로고
    • 16 Mb split gate flash memory with improved process window
    • J. Yater et al., "16 Mb split gate flash memory with improved process window," in Proc. IEEE Int. Memory Workshop (IMW), 2009, pp. 1-2.
    • Proc. IEEE Int. Memory Workshop (IMW), 2009 , pp. 1-2
    • Yater, J.1
  • 12
    • 84876517910 scopus 로고    scopus 로고
    • 40 nm embedded SG-MONOS flash macros for automotive with 160 MHz random access for code and endurance over 10 M cycles for data
    • T. Kono et al., "40 nm embedded SG-MONOS flash macros for automotive with 160 MHz random access for code and endurance over 10 M cycles for data," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2013, pp. 212-213.
    • IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2013 , pp. 212-213
    • Kono, T.1
  • 13
    • 0033681432 scopus 로고    scopus 로고
    • 1.25 volt, low cost, embedded flash memory for low density applications
    • R. McPartland and R. Singh, "1.25 volt, low cost, embedded flash memory for low density applications," in IEEE Symp. VLSI Circuits Dig., 2000, pp. 158-161.
    • IEEE Symp. VLSI Circuits Dig., 2000 , pp. 158-161
    • McPartland, R.1    Singh, R.2
  • 15
    • 0036564734 scopus 로고    scopus 로고
    • A system LSI memory redundancy technique using an IE-flash (inverse-gate-electrode flash) programming circuit
    • May
    • M. Yamaoka et al., "A system LSI memory redundancy technique using an IE-flash (inverse-gate-electrode flash) programming circuit," IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 599-604, May 2002.
    • (2002) IEEE J. Solid-State Circuits , vol.37 , Issue.5 , pp. 599-604
    • Yamaoka, M.1
  • 17
    • 78751490060 scopus 로고    scopus 로고
    • A PND (PMOS-NMOS-depletion MOS) type single poly gate non-volatilememory cell design with a differential cell architecture in a pure CMOS logic process for a system LSI
    • May
    • Y. Yamamoto et al., "A PND (PMOS-NMOS-depletion MOS) type single poly gate non-volatilememory cell design with a differential cell architecture in a pure CMOS logic process for a system LSI," IEICE Trans. Electron., vol. E90-C, no. 5, pp. 1129-1137, May 2007.
    • (2007) IEICE Trans. Electron. , vol.E90-C , Issue.5 , pp. 1129-1137
    • Yamamoto, Y.1
  • 18
    • 84892972656 scopus 로고    scopus 로고
    • Nonvolatile semiconductor memory device
    • US Patent 7,755,941, Jul. 13
    • Y. Yamamoto et al., "Nonvolatile semiconductor memory device," US Patent 7,755,941, Jul. 13, 2010.
    • (2010)
    • Yamamoto, Y.1
  • 19
    • 57149137492 scopus 로고    scopus 로고
    • Floating-gate nonvolatile memory with ultrathin 5 nm tunnel oxide
    • Dec.
    • Y. Ma et al., "Floating-gate nonvolatile memory with ultrathin 5 nm tunnel oxide," IEEE Trans. Electron Devices, vol. 55, no. 12, pp. 3476-3481, Dec. 2008.
    • (2008) IEEE Trans. Electron Devices , vol.55 , Issue.12 , pp. 3476-3481
    • Ma, Y.1
  • 20
    • 84886104647 scopus 로고    scopus 로고
    • PFET nonvolatile memory
    • US Patent 7,221,596, May 22
    • A. Pesavento, F. Bernard, and J. Hyde, "PFET nonvolatile memory," US Patent 7,221,596, May 22, 2007.
    • (2007)
    • Pesavento, A.1    Bernard, F.2    Hyde, J.3
  • 22
    • 84892654920 scopus 로고    scopus 로고
    • Single polysilicon layer non-volatile memory and operating method thereof
    • US Patent 8,199,578, Jun. 12
    • H. Chen et al., "Single polysilicon layer non-volatile memory and operating method thereof," US Patent 8,199,578, Jun. 12, 2012.
    • (2012)
    • Chen, H.1
  • 24
    • 84866618592 scopus 로고    scopus 로고
    • A logic-compatible embedded flash memory featuring a multi-story high voltage switch and a selective refresh scheme
    • S. Song, K. Chun, and C. H. Kim, "A logic-compatible embedded flash memory featuring a multi-story high voltage switch and a selective refresh scheme," in IEEE Symp. VLSI Circuits Dig., 2012, pp. 130-131.
    • IEEE Symp. VLSI Circuits Dig., 2012 , pp. 130-131
    • Song, S.1    Chun, K.2    Kim, C.H.3
  • 25
    • 0030291637 scopus 로고    scopus 로고
    • 2 3.3 V only 128 Mb multilevel NAND flash memory for mass storage applications
    • Nov.
    • 2 3.3 V only 128 Mb multilevel NAND flash memory for mass storage applications," IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1575-1583, Nov. 1996.
    • (1996) IEEE J. Solid-State Circuits , vol.31 , Issue.11 , pp. 1575-1583
    • Jung, T.1
  • 26
    • 0029404872 scopus 로고
    • A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme
    • Nov.
    • K. Suh et al., "A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme," IEEE J. Solid-State Circuits, vol. 30, no. 11, pp. 1149-1156, Nov. 1995.
    • (1995) IEEE J. Solid-State Circuits , vol.30 , Issue.11 , pp. 1149-1156
    • Suh, K.1
  • 27
    • 84860667742 scopus 로고    scopus 로고
    • Bitline-capacitance-cancelation sensing scheme with 11 ns read latency and maximum read throughput of 2.9 GB/s in 65 nm embedded flash for automotive
    • M. Jefremow et al., "Bitline-capacitance-cancelation sensing scheme with 11 ns read latency and maximum read throughput of 2.9 GB/s in 65 nm embedded flash for automotive," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2012, pp. 428-429.
    • IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2012 , pp. 428-429
    • Jefremow, M.1
  • 28
    • 0032028335 scopus 로고    scopus 로고
    • A high-efficiency CMOS voltage doubler
    • Mar.
    • P. Favrat, P. Deval, and M. Declercq, "A high-efficiency CMOS voltage doubler," IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 410-416, Mar. 1998.
    • (1998) IEEE J. Solid-State Circuits , vol.33 , Issue.3 , pp. 410-416
    • Favrat, P.1    Deval, P.2    Declercq, M.3
  • 29
    • 0038718671 scopus 로고    scopus 로고
    • Power efficient charge pump in deep submicron standard CMOS technology
    • Jun.
    • R. Pelliconi et al., "Power efficient charge pump in deep submicron standard CMOS technology," IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 1068-1071, Jun. 2003.
    • (2003) IEEE J. Solid-State Circuits , vol.38 , Issue.6 , pp. 1068-1071
    • Pelliconi, R.1
  • 31
    • 3342973263 scopus 로고
    • Relaxation of interface states and positive charge in thin gate oxide after Fowler-Nordheim stress
    • Apr.
    • A. Hdiy, G. Salace, and C. Petit, "Relaxation of interface states and positive charge in thin gate oxide after Fowler-Nordheim stress," AIP J. Appl. Phys., vol. 73, no. 7, pp. 3569-3570, Apr. 1993.
    • (1993) AIP J. Appl. Phys. , vol.73 , Issue.7 , pp. 3569-3570
    • Hdiy, A.1    Salace, G.2    Petit, C.3
  • 32
    • 0032097823 scopus 로고    scopus 로고
    • Degradation of thin tunnel gate oxide under constant Fowler-Nordheim current stress for a flash EEPROM
    • Jun.
    • Y. Park and D. Schroder, "Degradation of thin tunnel gate oxide under constant Fowler-Nordheim current stress for a flash EEPROM," IEEE Trans. Electron Devices, vol. 45, no. 6, pp. 1361-1368, Jun. 1998.
    • (1998) IEEE Trans. Electron Devices , vol.45 , Issue.6 , pp. 1361-1368
    • Park, Y.1    Schroder, D.2
  • 33
    • 0033360385 scopus 로고    scopus 로고
    • Detailed observation of small leak current in flash memories with thin tunnel oxides
    • May
    • Y. Manabe et al., "Detailed observation of small leak current in flash memories with thin tunnel oxides," IEEE Trans. Semicond. Manufact., vol. 12, no. 2, pp. 170-174, May 1999.
    • (1999) IEEE Trans. Semicond. Manufact. , vol.12 , Issue.2 , pp. 170-174
    • Manabe, Y.1
  • 34
    • 3142773890 scopus 로고    scopus 로고
    • Introduction to flash memory
    • Apr.
    • R. Bez et al., "Introduction to flash memory," Proc. IEEE, vol. 91, no. 4, Apr. 2003.
    • (2003) Proc. IEEE , vol.91 , Issue.4
    • Bez, R.1
  • 35
    • 2342522065 scopus 로고    scopus 로고
    • Effects of interface trap generation and annihilation on the data retention characteristics of flash memory cells
    • Mar.
    • J. Lee et al., "Effects of interface trap generation and annihilation on the data retention characteristics of flash memory cells," IEEE Trans. Device Mat. Rel., vol. 4, no. 1, pp. 110-117, Mar. 2004.
    • (2004) IEEE Trans. Device Mat. Rel. , vol.4 , Issue.1 , pp. 110-117
    • Lee, J.1
  • 36
    • 11144248077 scopus 로고    scopus 로고
    • Flash EEPROM threshold instabilities due to charge trapping during program/erase cycling
    • Sep.
    • N. Mielke et al., "Flash EEPROM threshold instabilities due to charge trapping during program/erase cycling," IEEE Trans. Device Mat. Rel., vol. 4, no. 3, pp. 335-344, Sep. 2004.
    • (2004) IEEE Trans. Device Mat. Rel. , vol.4 , Issue.3 , pp. 335-344
    • Mielke, N.1
  • 37
    • 84872085405 scopus 로고    scopus 로고
    • Quasi-nonvolatile SSD: Trading flash memory nonvolatility to improve storage system performance for enterprise applications
    • Y. Pan et al., "Quasi-nonvolatile SSD: Trading flash memory nonvolatility to improve storage system performance for enterprise applications," in Proc. IEEE Int. Symp. High Performance Comput. Architecture (HPCA), 2012, pp. 1-10.
    • Proc. IEEE Int. Symp. High Performance Comput. Architecture (HPCA), 2012 , pp. 1-10
    • Pan, Y.1
  • 39
  • 40
    • 84860676678 scopus 로고    scopus 로고
    • Over-10x-extended-lifetime 76%-reduced-error Solid-State Drives (SSDs) with error-prediction LDPC architecture and error-recovery scheme
    • S. Tanakamaru, Y. Yanagihara, and K. Takeuchi, "Over-10x-extended- lifetime 76%-reduced-error Solid-State Drives (SSDs) with error-prediction LDPC architecture and error-recovery scheme," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2012, pp. 424-425.
    • IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2012 , pp. 424-425
    • Tanakamaru, S.1    Yanagihara, Y.2    Takeuchi, K.3
  • 41
    • 0027840454 scopus 로고    scopus 로고
    • A new self-data-refresh scheme for a sector erasable 16 Mb flash EEPROM
    • A. Umezawa et al., "A new self-data-refresh scheme for a sector erasable 16 Mb flash EEPROM," in IEEE Symp. VLSI Circuits Dig., 1993, pp. 99-100.
    • IEEE Symp. VLSI Circuits Dig., 1993 , pp. 99-100
    • Umezawa, A.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.