CMOS process compatible ie-flash (inverse gate electrode flash) technology for system-on-a chip

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2001, Pages 179-182

  Shukuri, S ^a   Yanagisawa, K ^a   Ishibashi, K ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRODES; ELECTRONS; INTEGRATED CIRCUIT MANUFACTURE; LOGIC DEVICES; LOGIC GATES; MOSFET DEVICES; VOLTAGE CONTROL;

ELECTRICALLY PROGRAMMABLE READ ONLY MEMORY; INVERSE GATE ELECTRODE FLASH TECHNOLOGY; SINGLE POLY FLASH TECHNOLOGY; SYSTEM ON A CHIP;

PROM;

EID: 0034825932     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. A PROM element based on salicide agglomeration of poly fuses in a CMOS logic process
2. A single poly EEPROM cell structure for use in standard CMOS processes
3. 1.25 volt, low cost, embedded FLASH memory for low density applications
4. A new physical model for NVM data-retention time-to-failure