Floating-gate nonvolatile memory with ultrathin 5-nm tunnel oxide

IEEE Transactions on Electron Devices

Volumn 55, Issue 12, 2008, Pages 3476-3481

  Ma, Yanjun ^a   Deng, Rui ^a   Nguyen, H ^a   Wang, Bin ^a,b   Pesavento, Alberto ^a   Niset, M ^a   Paulsen, Ron ^a  

^a Impinj   (United States)

^b Virage Logic   (United States)

Author keywords

CMOS memory; EEPROM; Floating gate (FG); Reliability

Indexed keywords

RELIABILITY; TUNNELS;

CMOS MEMORY; CMOS PROCESSES; EEPROM; FLOATING GATE (FG); GATE OXIDES; INTRINSIC RETENTIONS; LOGIC PROCESSES; MEMORY CELLS; MEMORY USING; NONVOLATILE MEMORIES; PROCESS NODES; PROCESSING STEPS; TUNNEL OXIDE]; TUNNEL OXIDES;

DATA STORAGE EQUIPMENT;

EID: 57149137492     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2008.2006538     Document Type: Article

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