-
1
-
-
84880985625
-
Temperature and field interrelation study of low-k TDDB for cu interconnects with and without liner-new insights to the roles of cu for a competing breakdown process
-
F. Chen, M. Shinosky, J. Aitken, C.-C. Yang, and D. Edelstein, "Temperature and field interrelation study of low-k TDDB for cu interconnects with and without liner-new insights to the roles of cu for a competing breakdown process," in Reliability Physics Symposium (IRPS), 2013 IEEE International, pp. 2F. 2. 1-2F. 2. 7, 2013.
-
(2013)
Reliability Physics Symposium (IRPS), 2013 IEEE International
-
-
Chen, F.1
Shinosky, M.2
Aitken, J.3
Yang, C.-C.4
Edelstein, D.5
-
2
-
-
33645823407
-
The impact of multiple failure modes on estimating product field reliability
-
march-april
-
J. Carulli, J. M. and T. Anderson, "The impact of multiple failure modes on estimating product field reliability," Design Test of Computers, IEEE, vol. 23, pp. 118-126, march-april 2006.
-
(2006)
Design Test of Computers, IEEE
, vol.23
, pp. 118-126
-
-
Carulli, J.M.J.1
Anderson, T.2
-
3
-
-
79959521433
-
Design and experimental characterization of a new built-in defect-based testing technique to achieve zero defects in the automotive environment
-
V. Malandruccolo, M. Ciappa, H. Rothleitner, and W. Fichtner, "Design and experimental characterization of a new built-in defect-based testing technique to achieve zero defects in the automotive environment," Device and Materials Reliability, IEEE Transactions on, vol. 11, no. 2, pp. 349-357, 2011.
-
(2011)
Device and Materials Reliability, IEEE Transactions on
, vol.11
, Issue.2
, pp. 349-357
-
-
Malandruccolo, V.1
Ciappa, M.2
Rothleitner, H.3
Fichtner, W.4
-
4
-
-
84873202875
-
An experiment of burn-in time reduction based on parametric test analysis
-
N. Sumikawa, L.-C. Wang, and M. Abadir, "An experiment of burn-in time reduction based on parametric test analysis," in Test Conference (ITC), 2012 IEEE International, pp. 1-10, 2012.
-
(2012)
Test Conference (ITC), 2012 IEEE International
, pp. 1-10
-
-
Sumikawa, N.1
Wang, L.-C.2
Abadir, M.3
-
5
-
-
51549109166
-
Characterizing infant mortality in high volume manufacturing
-
A. Vassighi, R. Kacprowicz, C. Carranza, and W. Riordan, "Characterizing infant mortality in high volume manufacturing," in Reliability Physics Symposium, 2008. IRPS 2008. IEEE International, pp. 717-718, 2008.
-
(2008)
Reliability Physics Symposium, 2008. IRPS 2008. IEEE International
, pp. 717-718
-
-
Vassighi, A.1
Kacprowicz, R.2
Carranza, C.3
Riordan, W.4
-
6
-
-
33846118079
-
Designing reliable systems from unreliable components: The challenges of transistor variability and degradation
-
nov.-dec
-
S. Borkar, "Designing reliable systems from unreliable components: the challenges of transistor variability and degradation," Micro, IEEE, vol. 25, pp. 10-16, nov.-dec. 2005.
-
(2005)
Micro, IEEE
, vol.25
, pp. 10-16
-
-
Borkar, S.1
-
7
-
-
34250705286
-
Successful development and implementation of statistical outlier techniques on 90nm and 65nm process driver devices
-
K. Butler, S. Subramaniam, A. Nahar, J. Carulli, T. Anderson, and W. Daasch, "Successful development and implementation of statistical outlier techniques on 90nm and 65nm process driver devices," in Reliability Physics Symposium Proceedings, 2006. 44th Annual. , IEEE International, pp. 552-559, 2006.
-
(2006)
Reliability Physics Symposium Proceedings, 2006. 44th Annual. , IEEE International
, pp. 552-559
-
-
Butler, K.1
Subramaniam, S.2
Nahar, A.3
Carulli, J.4
Anderson, T.5
Daasch, W.6
-
9
-
-
77957927489
-
Method of deciding burn-in stress voltage in conceptual design phase
-
J. Y. Seo, N. S. Park, H.-J. Park, H. S. Park, W. S. Kim, S. Y. Lim, H. Kim, N. H. Cha, J. S. Kang, and B. S. So, "Method of deciding burn-in stress voltage in conceptual design phase," in Reliability Physics Symposium (IRPS), 2010 IEEE International, pp. 1004-1005, 2010.
-
(2010)
Reliability Physics Symposium (IRPS), 2010 IEEE International
, pp. 1004-1005
-
-
Seo, J.Y.1
Park, N.S.2
Park, H.-J.3
Park, H.S.4
Kim, W.S.5
Lim, S.Y.6
Kim, H.7
Cha, N.H.8
Kang, J.S.9
So, B.S.10
-
10
-
-
33645812150
-
Reducing burnin time through high-voltage stress test and weibull statistical analysis
-
M. Zakaria, Z. Kassim, M. Ooi, and S. Demidenko, "Reducing burnin time through high-voltage stress test and weibull statistical analysis," Design Test of Computers, IEEE, vol. 23, no. 2, pp. 88-98, 2006.
-
(2006)
Design Test of Computers, IEEE
, vol.23
, Issue.2
, pp. 88-98
-
-
Zakaria, M.1
Kassim, Z.2
Ooi, M.3
Demidenko, S.4
-
11
-
-
0030651768
-
SHOrt voltage elevation (SHOVE) test for weak CMOS ICs
-
J.-Y. Chang and E. McCluskey, "SHOrt voltage elevation (SHOVE) test for weak CMOS ICs," in VLSI Test Symposium, 1997. , 15th IEEE, pp. 446-451, 1997.
-
(1997)
VLSI Test Symposium, 1997. , 15th IEEE
, pp. 446-451
-
-
Chang, J.-Y.1
McCluskey, E.2
-
12
-
-
0036734082
-
IDDQ test: Will it survive the DSM challenge?
-
S. Sabade and D. Walker, "IDDQ test: will it survive the DSM challenge?," Design Test of Computers, IEEE, vol. 19, no. 5, pp. 8-16, 2002.
-
(2002)
Design Test of Computers, IEEE
, vol.19
, Issue.5
, pp. 8-16
-
-
Sabade, S.1
Walker, D.2
-
13
-
-
0030385618
-
Detecting delay flaws by very-lowvoltage testing
-
J.-Y. Chang and E. McCluskey, "Detecting delay flaws by very-lowvoltage testing," in Test Conference, 1996. Proceedings. , International, pp. 367-376, 1996.
-
(1996)
Test Conference, 1996. Proceedings. , International
, pp. 367-376
-
-
Chang, J.-Y.1
McCluskey, E.2
-
14
-
-
0035003540
-
Minvdd testing for weak cmos ics
-
C.-W. Tseng, R. Chen, P. Nigh, and E. McCluskey, "Minvdd testing for weak cmos ics," in VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001, pp. 339-344, 2001.
-
(2001)
VLSI Test Symposium, 19th IEEE Proceedings On. VTS 2001
, pp. 339-344
-
-
Tseng, C.-W.1
Chen, R.2
Nigh, P.3
McCluskey, E.4
-
15
-
-
0036445141
-
Comparison of iddq testing and very-low voltage testing
-
B. Kruseman, S. van den Oetelaar, and J. Rius, "Comparison of iddq testing and very-low voltage testing," in Test Conference, 2002. Proceedings. International, pp. 964-973, 2002.
-
(2002)
Test Conference, 2002. Proceedings. International
, pp. 964-973
-
-
Kruseman, B.1
Oetelaar Den S.Van2
Rius, J.3
-
16
-
-
51449088512
-
Statistical postprocessing at wafersort-an alternative to burn-in and a manufacturable solution to test limit setting for sub-micron technologies
-
R. Madge, M. Rehani, K. Cota, and W. Daasch, "Statistical postprocessing at wafersort-an alternative to burn-in and a manufacturable solution to test limit setting for sub-micron technologies," in VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE, pp. 69-74, 2002.
-
(2002)
VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE
, pp. 69-74
-
-
Madge, R.1
Rehani, M.2
Cota, K.3
Daasch, W.4
-
17
-
-
77953901218
-
Gateoxide early-life failure identification using delay shifts
-
april
-
Y. M. Kim, T. W. Chen, Y. Kameda, M. Mizuno, and S. Mitra, "Gateoxide early-life failure identification using delay shifts," in VLSI Test Symposium (VTS), 2010 28th, pp. 69-74, april 2010.
-
(2010)
VLSI Test Symposium (VTS), 2010 28th
, pp. 69-74
-
-
Kim, Y.M.1
Chen, T.W.2
Kameda, Y.3
Mizuno, M.4
Mitra, S.5
-
18
-
-
51449105667
-
Gate-oxide early life failure prediction
-
27-may 1 2008
-
T. W. Chen, K. Kim, Y. M. Kim, and S. Mitra, "Gate-oxide early life failure prediction," in VLSI Test Symposium, 2008. VTS 2008. 26th IEEE, pp. 111-118, 27 2008-may 1 2008.
-
(2008)
VLSI Test Symposium, 2008. VTS 2008. 26th IEEE
, pp. 111-118
-
-
Chen, T.W.1
Kim, K.2
Kim, Y.M.3
Mitra, S.4
-
19
-
-
77958002043
-
Low-cost gate-oxide early-life failure detection in robust systems
-
june
-
Y. M. Kim, Y. Kameda, H. Kim, M. Mizuno, and S. Mitra, "Low-cost gate-oxide early-life failure detection in robust systems," in VLSI Circuits (VLSIC), 2010 IEEE Symposium on, pp. 125-126, june 2010.
-
(2010)
VLSI Circuits (VLSIC), 2010 IEEE Symposium on
, pp. 125-126
-
-
Kim, Y.M.1
Kameda, Y.2
Kim, H.3
Mizuno, M.4
Mitra, S.5
-
20
-
-
84892652760
-
Detection of early-life failures in high-k metal-gate transistors and ultra low-k inter-metal dielectrics
-
(to appear)
-
Y. M. Kim, J. Seomun, H.-O. Kim, K.-T. Do, J. Y. Choi, K. S. Kim, M. Sauer, B. Becker, and S. Mitra, "Detection of early-life failures in high-k metal-gate transistors and ultra low-k inter-metal dielectrics," in Custom Integrated Circuits Conference (to appear), 2013.
-
(2013)
Custom Integrated Circuits Conference
-
-
Kim, Y.M.1
Seomun, J.2
Kim, H.-O.3
Do, K.-T.4
Choi, J.Y.5
Kim, K.S.6
Sauer, M.7
Becker, B.8
Mitra, S.9
-
22
-
-
84872341109
-
Small-delay-fault atpg with waveform accuracy
-
nov
-
M. Sauer, A. Czutro, I. Polian, and B. Becker, "Small-delay-fault ATPG with waveform accuracy," in Computer-Aided Design (ICCAD), 2012 IEEE/ACM International Conference on, pp. 30-36, nov. 2012.
-
(2012)
Computer-Aided Design (ICCAD), 2012 IEEE/ACM International Conference on
, pp. 30-36
-
-
Sauer, M.1
Czutro, A.2
Polian, I.3
Becker, B.4
-
23
-
-
79959954432
-
SAT-based analysis of sensitisable paths
-
april
-
M. Sauer, A. Czutro, T. Schubert, S. Hillebrecht, I. Polian, and B. Becker, "SAT-based analysis of sensitisable paths," in Design and Diagnostics of Electronic Circuits Systems (DDECS), 2011 IEEE 14th International Symposium on, pp. 93-98, april 2011.
-
(2011)
Design and Diagnostics of Electronic Circuits Systems (DDECS), 2011 IEEE 14th International Symposium on
, pp. 93-98
-
-
Sauer, M.1
Czutro, A.2
Schubert, T.3
Hillebrecht, S.4
Polian, I.5
Becker, B.6
-
24
-
-
84856167232
-
Efficient SATbased search for longest sensitisable paths
-
nov
-
M. Sauer, J. Jiang, A. Czutro, I. Polian, and B. Becker, "Efficient SATbased search for longest sensitisable paths," in Test Symposium (ATS), 2011 20th Asian, pp. 108-113, nov. 2011.
-
(2011)
Test Symposium (ATS), 2011 20th Asian
, pp. 108-113
-
-
Sauer, M.1
Jiang, J.2
Czutro, A.3
Polian, I.4
Becker, B.5
-
26
-
-
84885618032
-
Efficient SATbased dynamic compaction and relaxation for longest sensitizable paths
-
M. Sauer, S. Reimer, T. Schubert, I. Polian, and B. Becker, "Efficient SATbased dynamic compaction and relaxation for longest sensitizable paths," in Design, Automation Test in Europe Conference Exhibition (DATE), 2013, pp. 448-453, 2013.
-
(2013)
Design, Automation Test in Europe Conference Exhibition (DATE), 2013
, pp. 448-453
-
-
Sauer, M.1
Reimer, S.2
Schubert, T.3
Polian, I.4
Becker, B.5
-
27
-
-
84891505947
-
-
OpenSPARC Microprocessor
-
"OpenSPARC Microprocessor. " http://www.opensparc.net.
-
-
-
-
28
-
-
25844479330
-
Dielectric breakdown mechanisms in gate oxides
-
S. Lombardo, J. Stathis, B. Linder, K. L. Pey, F. Palumbo, and C.-H. Tung, "Dielectric breakdown mechanisms in gate oxides," Journal of Applied Physics, vol. 98, no. 12, pp. 121301-121301-36, 2005.
-
(2005)
Journal of Applied Physics
, vol.98
, Issue.12
, pp. 121301-12130136
-
-
Lombardo, S.1
Stathis, J.2
Linder, B.3
Pey, K.L.4
Palumbo, F.5
Tung, C.-H.6
-
30
-
-
84866603540
-
Hot carrier degradation: From defect creation modeling to their impact on NMOS parameters
-
Y. Randriamihaja, A. Zaka, V. Huard, M. Rafik, D. Rideau, D. Roy, A. Bravaix, and P. Palestri, "Hot carrier degradation: From defect creation modeling to their impact on NMOS parameters," in Reliability Physics Symposium (IRPS), 2012 IEEE International, pp. XT. 15. 1-XT. 15. 4, 2012.
-
(2012)
Reliability Physics Symposium (IRPS), 2012 IEEE International
, pp. 151-154
-
-
Randriamihaja, Y.1
Zaka, A.2
Huard, V.3
Rafik, M.4
Rideau, D.5
Roy, D.6
Bravaix, A.7
Palestri, P.8
-
31
-
-
70449134580
-
Critical ultra low-k TDDB reliability issues for advanced CMOS technologies
-
F. Chen, M. Shinosky, B. Li, J. Gambino, S. Mongeon, P. Pokrinchak, J. Aitken, D. Badami, M. Angyal, R. Achanta, G. Bonilla, G. Yang, P. Liu, K. Li, J. Sudijono, Y. Tan, T. J. Tang, and C. Child, "Critical ultra low-k TDDB reliability issues for advanced CMOS technologies," in Reliability Physics Symposium, 2009 IEEE International, pp. 464-475, 2009.
-
(2009)
Reliability Physics Symposium, 2009 IEEE International
, pp. 464-475
-
-
Chen, F.1
Shinosky, M.2
Li, B.3
Gambino, J.4
Mongeon, S.5
Pokrinchak, P.6
Aitken, J.7
Badami, D.8
Angyal, M.9
Achanta, R.10
Bonilla, G.11
Yang, G.12
Liu, P.13
Li, K.14
Sudijono, J.15
Tan, Y.16
Tang, T.J.17
Child, C.18
-
32
-
-
77953111813
-
An on-chip clock generation scheme for faster-than-at-speed delay testing
-
S. Pei, H. Li, and X. Li, "An on-chip clock generation scheme for faster-than-at-speed delay testing," in Design, Automation Test in Europe Conference Exhibition (DATE), 2010, pp. 1353-1356, 2010.
-
(2010)
Design, Automation Test in Europe Conference Exhibition (DATE), 2010
, pp. 1353-1356
-
-
Pei, S.1
Li, H.2
Li, X.3
-
33
-
-
77953904903
-
An output compression scheme for handling x-states from over-clocked delay tests
-
A. Singh, C. Han, and X. Qian, "An output compression scheme for handling x-states from over-clocked delay tests," in VLSI Test Symposium (VTS), 2010 28th, pp. 57-62, 2010.
-
(2010)
VLSI Test Symposium (VTS), 2010 28th
, pp. 57-62
-
-
Singh, A.1
Han, C.2
Qian, X.3
-
34
-
-
33751077362
-
Output hazard-free transition tests for silicon calibrated scan based delay testing
-
A. Singh and G. Xu, "Output hazard-free transition tests for silicon calibrated scan based delay testing," in VLSI Test Symposium, 2006. Proceedings. 24th IEEE, pp. 7 pp.-357, 2006.
-
(2006)
VLSI Test Symposium, 2006. Proceedings. 24th IEEE
, vol.7
, pp. 357
-
-
Singh, A.1
Xu, G.2
-
35
-
-
39749176233
-
At-speed structural test for high-performance asics
-
V. Iyengar, T. Yokota, K. Yamada, T. Anemikos, B. Bassett, M. Degregorio, R. Farmer, G. Grise, M. Johnson, D. Milton, M. Taylor, and F. Woytowich, "At-speed structural test for high-performance asics," in Test Conference, 2006. ITC '06. IEEE International, pp. 1-10, 2006.
-
(2006)
Test Conference, 2006. ITC '06. IEEE International
, pp. 1-10
-
-
Iyengar, V.1
Yokota, T.2
Yamada, K.3
Anemikos, T.4
Bassett, B.5
Degregorio, M.6
Farmer, R.7
Grise, G.8
Johnson, M.9
Milton, D.10
Taylor, M.11
Woytowich, F.12
-
36
-
-
84891528829
-
-
Cadence True-Time.
-
"Cadence True-Time.
-
-
-
-
37
-
-
67249129781
-
VAST: Virtualization-assisted concurrent autonomous self-test
-
oct
-
H. Inoue, Y. Li, and S. Mitra, "VAST: Virtualization-Assisted Concurrent Autonomous Self-Test," in Test Conference, 2008. ITC 2008. IEEE International, pp. 1-10, oct. 2008.
-
(2008)
Test Conference, 2008. ITC 2008. IEEE International
, pp. 1-10
-
-
Inoue, H.1
Li, Y.2
Mitra, S.3
-
38
-
-
49749112001
-
CASP: Concurrent autonomous chip self-test using stored test patterns
-
march
-
Y. Li, S. Makar, and S. Mitra, "CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns," in Design, Automation and Test in Europe, 2008. DATE '08, pp. 885-890, march 2008.
-
(2008)
Design, Automation and Test in Europe, 2008. DATE '08
, pp. 885-890
-
-
Li, Y.1
Makar, S.2
Mitra, S.3
-
39
-
-
77953883349
-
Concurrent autonomous selftest for uncore components in system-on-chips
-
april
-
Y. Li, O. Mutlu, D. Gardner, and S. Mitra, "Concurrent autonomous selftest for uncore components in system-on-chips," in VLSI Test Symposium (VTS), 2010 28th, pp. 232-237, april 2010.
-
(2010)
VLSI Test Symposium (VTS), 2010 28th
, pp. 232-237
-
-
Li, Y.1
Mutlu, O.2
Gardner, D.3
Mitra, S.4
-
40
-
-
84891503079
-
Self-repair of uncore components in robust system-on-chips: An opensparc t2 case study
-
Y. Li, E. Cheng, S. Makar, and S. Mitra, "Self-repair of uncore components in robust system-on-chips: An opensparc t2 case study," in Test Conference, 2013. ITC 2013. International, p. (to appear), 2013.
-
(2013)
Test Conference, 2013. ITC 2013. International
-
-
Li, Y.1
Cheng, E.2
Makar, S.3
Mitra, S.4
-
41
-
-
0023330236
-
Transition fault simulation
-
J. Waicukauski, E. Lindbloom, B. K. Rosen, and V. Iyengar, "Transition fault simulation," Design Test of Computers, IEEE, vol. 4, no. 2, pp. 32-38, 1987.
-
(1987)
Design Test of Computers, IEEE
, vol.4
, Issue.2
, pp. 32-38
-
-
Waicukauski, J.1
Lindbloom, E.2
Rosen, B.K.3
Iyengar, V.4
-
43
-
-
84944406286
-
Counterexampleguided abstraction refinement
-
Springer
-
E. Clarke, O. Grumberg, S. Jha, Y. Lu, and H. Veith, " Counterexampleguided abstraction refinement," in Computer Aided Verification, pp. 154-169, Springer, 2000.
-
(2000)
Computer Aided Verification
, pp. 154-169
-
-
Clarke, E.1
Grumberg, O.2
Jha, S.3
Lu, Y.4
Veith, H.5
-
44
-
-
84891524463
-
-
Nangate 45nm Open Cell Library
-
"Nangate 45nm Open Cell Library. " http://www.nangate.com.
-
-
-
|