Detecting delay flaws by very-low-voltage testing

IEEE International Test Conference (TC)

Volumn , Issue , 1996, Pages 367-376

  Chang, Jonathan T Y ^a   McCluskey, Edward J ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DEFECTS; GATES (TRANSISTOR); THRESHOLD LOGIC; TRANSISTORS;

DELAY FLAWS; LOW VOLTAGE TESTING;

INTEGRATED CIRCUIT TESTING;

EID: 0030385618     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)