Low-cost gate-oxide early-life failure detection in robust systems

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2010, Pages 125-126

  Moon Kim, Young ^a   Kameda, Yoshio ^b   Kim, Hyunki ^a   Mizuno, Masayuki ^b   Mitra, Subhasish ^a,c  

^a Electrical Engineering   (Japan)

^b Stanford University   (Japan)

^c NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATIONAL LOGIC CIRCUITS; CONCURRENT ERROR DETECTION; FAILURE DETECTION; FUNCTIONAL FAILURE; GATE OXIDE; ON-CHIP CLOCKS; ROBUST SYSTEMS; SELF-TEST; TEST CHIPS;

ERROR DETECTION; LOGIC CIRCUITS; SWITCHING CIRCUITS;

VLSI CIRCUITS;

EID: 77958002043     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2010.5560326     Document Type: Conference Paper

References (10)

1. S. Borkar, IEEE Micro (05).
2. IEEE Design & Test, Special Issue on Reliability Defect Screening (06).
3. Y. Li, et al., DATE (08).
4. H. Inoue, et al., ITC (08).
5. Y. Li, et al., ICCAD (09).
6. T. Nakura, et al., ISSCC (07).
7. P. Mahoney, et al., ISSCC (05).
8. R. Ho, et al., VLSI Circuits Symp. (98).
9. T. Chen, et al., VTS (08).
10. T. Chen, et al., IRPS (09).