MINVDD testing for weak CMOS ICs

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2001, Pages 339-344

  Tseng, C W ^a   Chen, R ^a   Nigh, P ^a   McCluskey, E J ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; FAILURE ANALYSIS; GATES (TRANSISTOR); INTEGRATED CIRCUIT MANUFACTURE; LOGIC GATES; THRESHOLD VOLTAGE;

CIRCUIT UNDER TEST; GATE OXIDE; LOW VOLTAGE TESTING; TEST TIMING;

INTEGRATED CIRCUIT TESTING;

EID: 0035003540     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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