At-speed structural test for high-performance ASICs

Proceedings - International Test Conference

Volumn , Issue , 2006, Pages

  Iyengar, Vikram ^a   Yokota, Toshihiko ^b   Yamada, Kazuhiro ^b   Anemikos, Theo ^a   Bassett, Bob ^a   Degregorio, Mike ^a   Farmer, Rudy ^a   Grise, Gary ^a   Johnson, Mark ^a   Milton, Dave ^a   Taylor, Mark ^a   Woytowich, Frank ^a  

^a IBM MICROELECTRONICS   (United States)

^b IBM JAPAN LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; DELAY CIRCUITS; LOGIC CIRCUITS; MEASUREMENT THEORY;

CIRCUIT DESIGN; HARDWARE MEASUREMENTS; OFF-SCAN CLOCKING; SEQUENTIAL LOGIC;

INTEGRATED CIRCUITS;

EID: 39749176233     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2006.297686     Document Type: Conference Paper

References (23)