Comparison of IDDQ testing and very-low voltage testing

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 964-973

  Kruseman, Bram ^a   Van den Oetelaar, Stefan ^a   Rius, Josep ^b  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIGITAL FILTERS; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; MOS DEVICES; THRESHOLD VOLTAGE;

DEEP SUB-MICRON TESTING; STATIC VOLTAGE-BASED TESTING; STUCK-AT FAULT MODEL; VERY-LOW VOLTAGE TESTING;

INTEGRATED CIRCUIT TESTING;

EID: 0036445141     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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