Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2013, Pages

  Kim, Young Moon ^a   Seomun, Jun ^b   Kim, Hyung Ock ^b   Do, Kyung Tae ^b   Choi, Jung Yun ^b   Kim, Kee Sup ^b   Sauer, Matthias ^b   Becker, Bernd ^c   Mitra, Subhasish ^a  

^a Stanford University   (United States)

^b SAMSUNG Electronics   (South Korea)

^c UNIVERSITY OF FREIBURG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC MATERIALS; INTEGRATED CIRCUITS;

CLOCK CONTROL; ERROR-DETECTION TECHNIQUES; INTER-METAL DIELECTRICS; ONLINE OPERATIONS; PRODUCTION TEST; ROBUST SYSTEMS; STRESS LEVELS; ULTRA LOW-K;

GATE DIELECTRICS;

EID: 84892652760     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2013.6658544     Document Type: Conference Paper

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