3-D-TCAD-based parasitic capacitance extraction for emerging multigate devices and circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 21, Issue 11, 2013, Pages 2094-2105

  Bhoj, Ajay N ^a   Joshi, Rajiv V ^b   Jha, Niraj K ^a  

^a Princeton University   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Device simulation; multigate field effect transistor (FET); parasitic capacitance; process simulation

Indexed keywords

ANALYSIS-BASED APPROACHES; CAPACITANCE SCALING; DEVICE SIMULATIONS; FUTURE TECHNOLOGIES; PARASITIC CAPACITANCE; PROCESS SIMULATIONS; STRUCTURE SYNTHESIS; TECHNOLOGY SCALING;

EXTRACTION; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUITS; NANOTECHNOLOGY;

CAPACITANCE;

EID: 84884910041     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2012.2227848     Document Type: Article

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