Sub-25nm FinFET with advanced fin formation and short channel effect engineering

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2011, Pages 14-15

  Yamashita, T ^a   Basker, V S ^a   Standaert, T ^a   Yeh, C C ^a   Yamamoto, T ^c   Maitra, K ^b   Lin, C H ^d   Faltermeier, J ^a   Kanakasabapathy, S ^a   Wang, M ^a   Sunamura, H ^c   Jagannathan, H ^a   Reznicek, A ^a   Schmitz, S ^a   Inada, A ^c   Wang, J ^a   Adhikari, H ^b   Berliner, N ^a   Lee, K L ^d   Kulkarni, P ^a   Zhu, Y ^d   Kumar, A ^d   Bryant, A ^a   Wu, S ^a   Kanarsky, T ^a   Cho, J ^b   McLellan, E ^a   Holmes, S J ^a   Johnson, R C ^a   Levin, T ^a   Demarest, J ^a   Li, J ^a   Oldiges, P ^a   Arnold, J ^a   Colburn, M ^a   Hane, M ^c   Mcherron, D ^a   Paruchuri, V K ^a   Doris, B ^a   Miller, R J ^b   Bu, H ^a   Khare, M ^a   O'Neill, J ^a   Leobandung, E ^a   more..

^a IBM RESEARCH   (United States)

^b IBM MICROELECTRONICS   (United States)

^c RENESAS TECHNOLOGY CORP   (Japan)

^d IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE AREA; DEVICE PERFORMANCE; DOPING TECHNIQUES; DUAL WORK FUNCTION; FIN PITCH; FINFET DEVICES; GATE STACKS; MANUFACTURABILITY; PROCESS FLOWS; SCAN CHAIN; SELF-HEATING; SHORT-CHANNEL EFFECT; YIELD IMPROVEMENT;

GATES (TRANSISTOR); INTEGRATED CIRCUIT TESTING; INTEGRATED CIRCUITS; OPTIMIZATION;

FINS (HEAT EXCHANGE);

EID: 80052677137     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. W. Haensch et al., IBM J. Res. Dev., vol. 50, p. 339, 2006.
2. J. Kavalieros et al., Symp. VLSI Tech.,p. 50, 2006.
3. V.S. Basker et al., Symp. VLSI Tech., p. 19, 2010.
4. C.C. Wu et al., IEDM Tech. Dig., p. 600, 2010
5. C.C. Yeh et al., IEDM Tech. Dig., p. 772, 2010