Analysis of parasitic resistance in double gate FinFETs with different fin lengths

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2011, Pages

  Yang, X ^a   Maitra, K ^a   Yeh, C ^b   Zeitzoff, P ^c   Raymond, M ^a   Kulkarni, P ^b   Wang, M ^b   Yamashita, T ^b   Basker, V S ^b   Standaert, T E ^b   Samavedam, S ^a   Bu, H ^b   Miller, R J ^a  

^a IBM MICROELECTRONICS   (United States)

^b IBM RESEARCH   (United States)

^c TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYTICAL MODEL; CHARACTERISTIC LENGTH; DOUBLE GATE; EXPERIMENTAL DATA; FIN LENGTH; FINFETS; PARASITIC RESISTANCES; RESISTANCE CHANGE;

MATHEMATICAL MODELS;

FINS (HEAT EXCHANGE);

EID: 83455169109     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOI.2011.6081799     Document Type: Conference Paper

References (5)

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2. T. Matsukawa, K. Endo, Y. Ishikawa, H. Yamauchi, S. O'uchi, Y. Liu, J. Tsukada, K. Ishii, K. Sakamoto, E. Suzuki, and M. Masahara, "Fluctuation Analysis of Parasitic Resistance in FinFETs With Scaled Fin Thickness," IEEE Electron Device Letters, vol. 30, no. 4, pp. 407-409, 2009.
3. A. Dixit, A. Kottantharayil, N. Collaert, M. Goodwin, M. Jurczak, and K. De Meyer, IEEE Trans. on Electron Devices, vol. 52, no. 6, pp. 1132-1140, 2005.
4. D. Tekleab, S. Samavedam, and P. Zeitzoff, "Modeling and Analysis of Parasitic Resistance in Double-Gate FinFETs," IEEE Trans. on Electron Devices, vol. 56, no. 10, pp. 2291-2296, 2009.
5. V. S. Basker, T. Standaert, H. Kawasaki, C.-C. Yeh, K. Maitra, T. Yamashita, J. Faltermeier, H. Adhikari, H. Jagannathan, J. Wang, H. Sunamura, S. Kanakasabapathy, S. Schmitz, J. Cummings, A. Inada, C.-H. Lin, P. Kulkarni, Y. Zhua, J. Kuss, T. Yamamoto, A. Kumara, J. Wahl, A. Yagishita, L. F. Edge, R. H. Kim, E. Mclellan, S. J. Holmes, M. Takayanagi, M. Colburn, V. K. Paruchuri, R. J. Miller, H. Bu, B. Doris, D. McHerron, E. Leobandung, and J. O'Neill, "A 0.063 μm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch," in VLSI Symp. Tech. Dig. pp. 19-20, 2010.