-
1
-
-
80054983694
-
-
May 4
-
D. Scansen, "Intel putting fins on at 22 nm", EETimes, http://www.eetimes.com/electronics-blogs/dew-point/4215728/Intel-putting-fins- on-at-22-nm, May 4, 2011.
-
(2011)
Intel Putting Fins on at 22 Nm
-
-
Scansen, D.1
-
2
-
-
33748582367
-
Silicon CMOS devices beyond scaling
-
W. Haensch, et al., "Silicon CMOS devices beyond scaling", IBM J. Res. Dev., vol. 50, p. 339, 2006.
-
(2006)
IBM J. Res. Dev.
, vol.50
, pp. 339
-
-
Haensch, W.1
-
3
-
-
84888401584
-
-
advanced 1D and 2D process simulator
-
Synopsys "Taurus-TSUPREM-4" advanced 1D and 2D process simulator, http://www.synopsys.com/Tools/TCAD/ProcessSimulation/Pages/ TaurusTSupreme4.aspx.
-
Taurus-TSUPREM-4
-
-
-
4
-
-
0000318215
-
A new three-dimensional device simulation formulation
-
E. Buturla, et al., "A new three-dimensional device simulation formulation," NASECODE VI Proc., pp. 291-296, 1989.
-
(1989)
NASECODE VI Proc.
, pp. 291-296
-
-
Buturla, E.1
-
5
-
-
6344251261
-
Efficient quantum correction model for multidimensional CMOS simulations
-
M. Ieong, et al., "Efficient quantum correction model for multidimensional CMOS simulations," Proc. SISPAD, pp. 129-132, 1998.
-
(1998)
Proc. SISPAD
, pp. 129-132
-
-
Ieong, M.1
-
7
-
-
0036923355
-
The effective drive current in CMOS inverters
-
paper 5.4.1 Dec.
-
M.H. Na, et al., "The effective drive current in CMOS inverters", IEDM Tech. Dig., paper 5.4.1, pp. 121-124, Dec. 2002.
-
(2002)
IEDM Tech. Dig.
, pp. 121-124
-
-
Na, M.H.1
-
8
-
-
0036923355
-
The effective drive current in CMOS inverters
-
paper 5.4.1 Dec.
-
M.H. Na, et al., "The effective drive current in CMOS inverters", IEDM Tech. Dig., paper 5.4.1, pp. 121-124, Dec. 2002.
-
(2002)
IEDM Tech. Dig.
, pp. 121-124
-
-
Na, M.H.1
-
9
-
-
80054969420
-
Comprehensive simulation study of statistical variability in 32nm SOI MOSFET
-
17-19 January, Granada, Spain
-
N. M. Idris, et al., "Comprehensive simulation study of statistical variability in 32nm SOI MOSFET", 7th Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits (EUROSOI), 17-19 January, Granada, Spain, 2011.
-
(2011)
7th Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits (EUROSOI)
-
-
Idris, N.M.1
-
10
-
-
80054999284
-
Modeling of width-quantization-induced variation in logic FinFETs for 22nm and beyond
-
paper 2A-3, June
-
C-H. Lin et al., "Modeling of width-quantization-induced variation in logic FinFETs for 22nm and beyond", VLSI Symp. on Tech. Dig., paper 2A-3, June 2011.
-
(2011)
VLSI Symp. on Tech. Dig.
-
-
Lin, C.-H.1
-
12
-
-
0033714120
-
Modeling line edge roughness effects in sub 100 nanometer gate length devices
-
Sept.
-
P. Oldiges, et al., "Modeling line edge roughness effects in sub 100 nanometer gate length devices", proc. SISPAD, pp. 131-134, Sept. 2000.
-
(2000)
Proc. SISPAD
, pp. 131-134
-
-
Oldiges, P.1
-
13
-
-
78650760269
-
Modeling and analysis of grain-orientation effects in emerging metal-gate devices and implications for SRAM reliability
-
paper 29.6 Dec.
-
H. Dadgour, et al., "Modeling and analysis of grain-orientation effects in emerging metal-gate devices and implications for SRAM reliability", IEDM Tech. Dig., paper 29.6, pp. 705-708, Dec. 2008.
-
(2008)
IEDM Tech. Dig.
, pp. 705-708
-
-
Dadgour, H.1
-
14
-
-
80055006517
-
Statistical simulation of metal-gate work-function fluctuation in emerging high-K/metal-gate CMOS devices
-
paper 9A-4, Sept.
-
C. Yu, et al., "Statistical simulation of metal-gate work-function fluctuation in emerging High-K/Metal-Gate CMOS devices", Proc. SISPAD, paper 9A-4, Sept. 2010.
-
(2010)
Proc. SISPAD
-
-
Yu, C.1
-
15
-
-
50949095861
-
Simulation of phonon-limited mobility for nano-scale si-based n-type non-planar device under general orientation and stress condition
-
K. Xiu, "Simulation of phonon-limited mobility for nano-scale Si-based n-type non-planar device under general orientation and stress condition", Journal of Computational Electronics, Vol. 7, No. 3, 172-175, 2009.
-
(2009)
Journal of Computational Electronics
, vol.7
, Issue.3
, pp. 172-175
-
-
Xiu, K.1
-
16
-
-
78649947718
-
Understanding mobility mechanisms in extremely scaled HfO2 (EOT 0.42 nm) using remote interfacial layer scavenging technique and vt-tuning dipoles with gate-first process
-
paper 17-1, Dec.
-
T. Ando, et al., "Understanding mobility mechanisms in extremely scaled HfO2 (EOT 0.42 nm) using remote interfacial layer scavenging technique and Vt-tuning dipoles with gate-first process", IEDM Tech. Dig., paper 17-1, Dec. 2009.
-
(2009)
IEDM Tech. Dig.
-
-
Ando, T.1
-
17
-
-
0035504954
-
Effective electron mobility in si inversion layers in MOS systems with a high-κ insulator: The role of remote phonon scattering
-
M.V. Fischetti, et al., "Effective electron mobility in Si inversion layers in MOS systems with a high-κ insulator: The role of remote phonon scattering", J. Appl. Phys. 90, 4587-4608, 2001.
-
(2001)
J. Appl. Phys.
, vol.90
, pp. 4587-4608
-
-
Fischetti, M.V.1
-
18
-
-
0012258244
-
Ballistic FET modeling using QDAME: Quantum device analysis by modal evaluation
-
Dec.
-
S.E. Laux, et al., "Ballistic FET modeling using QDAME: Quantum Device Analysis by Modal Evaluation," IEEE Trans. Nanotech., vol. 1, pp. 255-259, Dec. 2002.
-
(2002)
IEEE Trans. Nanotech.
, vol.1
, pp. 255-259
-
-
Laux, S.E.1
-
19
-
-
2942571688
-
Analysis of quantum ballistic transport in ultra-small silicon devices including space-charge and geometric effects
-
May
-
S.E. Laux, et al., "Analysis of quantum ballistic transport in ultra-small silicon devices including space-charge and geometric effects," J. Appl. Phys., vol. 95, pp. 5545-5582, May 2004.
-
(2004)
J. Appl. Phys.
, vol.95
, pp. 5545-5582
-
-
Laux, S.E.1
-
20
-
-
0024070809
-
Monte Carlo simulation of submicron si n-MOSFETs at 77 and 300 K
-
September
-
S. E. Laux, et al., "Monte Carlo simulation of submicron Si n-MOSFETs at 77 and 300 K", IEEE Electron Device Letters, vol. 9, No. 9, pp. 467-469, September, 1988.
-
(1988)
IEEE Electron Device Letters
, vol.9
, Issue.9
, pp. 467-469
-
-
Laux, S.E.1
|