A 0.021 μm2 trigate SRAM cell with aggressively scaled gate and contact pitch

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2011, Pages 64-65

  Guillorn, M A ^a   Chang, J ^a   Pyzyna, A ^a   Engelmann, S ^a   Glodde, M ^a   Joseph, E ^a   Bruce, R ^a   Ott, J A ^a   Majumdar, A ^a   Liu, F ^a   Brink, M ^a   Bangsaruntip, S ^a   Khater, M ^a   Mauer, S ^a   Lauer, I ^a   Lavoie, C ^a   Zhang, Z ^a   Newbury, J ^a   Kratschmer, E ^a   Klaus, D P ^a   Bucchignano, J ^a   To, B ^a   Graham, W ^a   Sikorski, E ^a   Narayanan, V ^a   Fuller, N ^a   Haensch, W ^a   more..

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

6T-SRAM; CMOS TECHNOLOGY; CONTACTED GATE PITCH; DEVICE ARCHITECTURES; FIN PITCH; MODULE INTEGRATION; SRAM CELL; TARGET TECHNOLOGY; TRIGATE;

CMOS INTEGRATED CIRCUITS;

TECHNOLOGY;

EID: 80052685134     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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5. M.A. Guillorn, et al, VLSI 2008.
6. M. Glodde, et al, SPIE 2011
7. Z. Zhang et al, APL, 97, 252108 (2010)