Transport-analysis-based 3-D TCAD capacitance extraction for sub-32-nm SRAM structures

IEEE Electron Device Letters

Volumn 33, Issue 2, 2012, Pages 158-160

  Bhoj, Ajay N ^a,b   Joshi, Rajiv V ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b Princeton University   (United States)

Author keywords

Parasitic capacitance; semiconductor device modeling; SRAM

Indexed keywords

6T-SRAM; BACK END OF THE LINES; CAPACITANCE EXTRACTION; ELECTRICAL BEHAVIORS; HIGH FREQUENCY; MEASURED DATA; MULTICELL; NANOSCALE CIRCUITS; PARASITIC CAPACITANCE; SEMICONDUCTOR DEVICE MODELING; TECHNOLOGY COMPUTER AIDED DESIGN;

CAPACITANCE; COMPUTER AIDED DESIGN; SEMICONDUCTING SILICON; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DEVICE STRUCTURES; STATIC RANDOM ACCESS STORAGE;

THREE DIMENSIONAL;

EID: 84856296776     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2011.2175359     Document Type: Article

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