Scaling of SOI FinFETs down to fin width of 4 nm for the 10nm technology node

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2011, Pages 12-13

  Chang, J B ^a   Guillorn, M ^a   Solomon, P M ^a   Lin, C H ^a   Engelmann, S U ^a   Pyzyna, A ^a   Ott, J A ^a   Haensch, W E ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FIN PITCH; FIN WIDTHS; FINFETS; FUNDAMENTAL LIMITS; GATE LENGTH; PERFORMANCE DEGRADATION; SOI FINFETS; TECHNOLOGY NODES;

CAPACITANCE MEASUREMENT; GATES (TRANSISTOR); INTEGRATED CIRCUITS;

FINS (HEAT EXCHANGE);

EID: 80052656398     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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