A 0.063 μm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2010, Pages 19-20

  Basker, V S ^a   Standaert, T ^a   Kawasaki, H ^a,c   Yeh, C C ^a   Maitra, K ^a,b   Yamashita, T ^a   Faltermeier, J ^a   Adhikari, H ^a,b   Jagannathan, H ^a   Wang, J ^a   Sunamura, H ^a,d   Kanakasabapathy, S ^a   Schmitz, S ^a   Cummings, J ^a   Inada, A ^a,d   Lin, C H ^a   Kulkarni, P ^a   Zhua, Y ^a,e   Kuss, J ^a   Yamamoto, T ^a,d   Kumara, A ^a,e   Wahl, J ^a   Yagishita, A ^a,c   Edge, L F ^a   Kim, R H ^a,b   McLellan, E ^a   Holmes, S J ^a   Johnson, R C ^a   Levin, T ^a   Demarest, J ^a   Hane, M ^a,d   Takayanagi, M ^a,c   Colburn, M ^a   Paruchuri, V K ^a   Miller, R J ^a,b   Bu, H ^a   Doris, B ^a   McHerron, D ^a   Leobandung, E ^a   O'Neill, J ^a   more..

^a IBM RESEARCH   (United States)

^b IBM MICROELECTRONICS   (United States)

^c Toshiba America Inc   (United States)

^d RENESAS TECHNOLOGY CORP   (Japan)

^e IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONTACTED GATE PITCH; CONVENTIONAL LITHOGRAPHY; EXTERNAL RESISTANCE; FIN PITCH; GATE LENGTH; IMAGE TRANSFER; INTEGRATION SCHEME; METAL GATE STACK; OPTICAL LITHOGRAPHY; SHORT CHANNELS; SRAM CELL;

EPITAXIAL GROWTH; FINS (HEAT EXCHANGE); INTEGRATED CIRCUITS; PHOTOLITHOGRAPHY; STATIC RANDOM ACCESS STORAGE;

EPITAXIAL FILMS;

EID: 77957867586     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2010.5556135     Document Type: Conference Paper

References (4)

1. B. Haran et al., IEDM, p. 625, 2008.
2. W. Haensch et al., IBM J. Res. Dev., vol. 50, p. 339, 2006.
3. J. Kavalieros et al., Symp. VLSI Tech., p. 50, 2006.
4. M. Guillorn et al., IEDM, p. 961, 2009.