Efficient methodologies for 3-D TCAD modeling of emerging devices and circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 32, Issue 1, 2013, Pages 47-58

  Bhoj, Ajay N ^a   Joshi, Rajiv V ^b   Jha, Niraj K ^a  

^a Princeton University   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Capacitance extraction; device simulation; process simulation; structure synthesis; technology CAD

Indexed keywords

CAPACITANCE EXTRACTION; DEVICE SIMULATIONS; PROCESS SIMULATIONS; STRUCTURE SYNTHESIS; TECHNOLOGY CAD;

COMPUTER AIDED DESIGN; FIELD EFFECT TRANSISTORS; ITERATIVE METHODS; OSCILLATORS (ELECTRONIC); STATIC RANDOM ACCESS STORAGE;

COMPUTER SIMULATION;

EID: 84871981217     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2012.2210421     Document Type: Article

References (19)

1. E. J. Nowak, I. Aller, T. Ludwig, K. Kim, R. V. Joshi, C.-T. Chuang, K. Bernstein, and R. Puri, "Turning silicon on its edge," IEEE Circuits Devices Mag., vol. 20, no. 1, pp. 20-31, Jan.-Feb. 2004.
2. H.-S. P. Wong, "Beyond the conventional transistor," IBM J. Res. Develop., vol. 46, nos. 2-3, pp. 133-168, Mar.-May 2002. (Pubitemid 34692345)
3. Z. Essa, P. Boulenc, C. Tavernier, F. Hirigoyen, A. Crocherie, J. Michelot, and D. Rideau, "3D TCAD simulation of advanced CMOS image sensors," in Proc. Int. Conf. Simul. Semicond. Processes Devices, Sep. 2011, pp. 187-190.
4. A. Zaka, J. Singerb, E. Dornelc, D. Garettoc, D. Rideaua, Q. Rafhayb, R. Clercb, J.-P. Manceauc, N. Degorsc, C. Boccaccioa, C. Taverniera, and H. Jaouen, "Characterization and 3D TCAD simulation of NOR-type flash non-volatile memories with emphasis on corner effects," Solid-State Electron., vol. 63, no. 1, pp. 158-162, Sep. 2011.
5. W. Wang, S. Chang, J. Huang, and S. Kuang, "3D TCAD simulations of strained Si CMOS devices with silicon-based alloy stressors and stressed CESL," Solid-State Electron., vol. 53, no. 8, pp. 880-887, Aug. 2009.
6. G. Pei, J. Kedzierski, P. Oldiges, M. Ieong, and E. Kan, "FinFET design considerations based on 3D TCAD simulation and analytical modeling," IEEE Trans. Electron Devices, vol. 49, no. 8, pp. 1411-1419, Aug. 2002.
7. M. Nawaz, W. Molzer, S. Decker, L. Giles, and T. Schulz, "On the device design assessment of multigate FETs (MuGFETs) using full process and device simulation in 3D TCAD," Microelectron. J., vol. 38, no. 12, pp. 1238-1251, Dec. 2007. (Pubitemid 350160752)
8. L. Sponton, L. Bomholt, and W. Fichtner, "Analysis of process-geometry modulations through 3D TCAD," in Proc. Int. Conf. Simul. Semicond. Processes Devices, Sep. 2007, pp. 385-388.
9. P. Fleischmann, R. Sabelka, A. Stach, R. Strasser, and S. Selberherr, "Grid generation for three-dimensional process and device simulation," in Proc. Int. Conf. Simul. Semicond. Processes Devices, Sep. 1996, pp. 161-166.
10. W. Wessner, J. Cervenka, C. Heitzinger, A. Hossinger, and S. Selberherr, "Anisotropic mesh refinement for the simulation of three-dimensional semiconductor manufacturing processes," IEEE Trans. Comput.-Aided Des., vol. 25, no. 10, pp. 2129-2139, Oct. 2006.
11. K. K. H. Toh, A. R. Neureuther, and E. W. Scheckler, "Algorithms for simulation of three-dimensional etching," IEEE Trans. Comput.-Aided Des., vol. 13, no. 5, pp. 616-624, May 1994.
12. Z. F. Zhou, Q. A. Huang, W. H. Li, and W. Lu, "A novel 3-D dynamic cellular automata model for photoresist-etching process simulation," IEEE Trans. Comput.-Aided Des., vol. 26, no. 1, pp. 100-114, Jan. 2007.
13. A. N. Bhoj and R. V. Joshi, "Transport analysis based 3D TCAD capacitance extraction for sub-32nm SRAM structures," IEEE Electron Device Lett., vol. 33, no. 2, pp. 158-160, Feb. 2012.
14. Sentaurus Structure Editor Manuals [Online]. Available: http://www. synopsys.com
15. Cadence SKILL Scripting Language [Online]. Available: http://www. cadence.com
16. Sentaurus TCAD Tool Suite [Online]. Available: http://www.synopsys. com
17. Sentaurus Process Manuals [Online]. Available: http://www.synopsys. com
18. Sentaurus TCAD Application Examples and Notes [Online]. Available: http://solvnet.synopsys.com
19. A. N. Bhoj, R. V. Joshi, S. Polonsky, R. Kanj, S. Saroop, Y. Tan, and N. K. Jha, "Hardware-assisted 3D TCAD for predictive capacitance extraction in 32 nm SOI SRAMs," in Proc. Int. Electron Devices Meet., Dec. 2011, pp. 173-174.