Analysis of the effects of fringing electric field on finFET device performance and structural optimization using 3-D simulation

IEEE Transactions on Electron Devices

Volumn 55, Issue 5, 2008, Pages 1177-1184

  Zhao, Hui ^a   Yeo, Yee Chia ^a,b,c   Rustagi, Subhash C ^b   Samudra, Ganesh Shankar ^c  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

^c Agency for Science   (Singapore)

Author keywords

Capacitance; FinFET; Fringing electric field; Simulation

Indexed keywords

CAPACITANCE; DIELECTRIC MATERIALS; ELECTRIC FIELDS; GATES (TRANSISTOR); LEAKAGE CURRENTS;

FIN WIDTH; FRINGING ELECTRIC FIELD; GATE HEIGHT; GATE-DIELECTRIC THICKNESS; PARASITIC CAPACITANCE; SPACER WIDTH;

FIELD EFFECT TRANSISTORS;

EID: 43949124548     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2008.919308     Document Type: Article

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