Study of through-silicon-via impact on the 3-D stacked ic layout

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 21, Issue 5, 2013, Pages 862-874

  Kim, Dae Hyun ^a   Athikulwongse, Krit ^a   Lim, Sung Kyu ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

3 D integrated chip (IC); interconnect; placement; routing; through silicon via (TSV)

Indexed keywords

INTEGRATED CHIPS; INTERCONNECT; PLACEMENT; ROUTING; THROUGH-SILICON VIA;

ALGORITHMS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUITS;

ELECTRONICS PACKAGING;

EID: 84876795136     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2012.2201760     Document Type: Article

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