Fast electroplating TSV process development for the via-last approach

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2010, Pages 777-780

  Li, H Y ^a   Liao, E ^a   Pang, X F ^a   Yu, H ^b   Yu, X X ^b   Sun, J Y ^b  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b Shanghai Sinyang Semiconductor Materials Co Ltd   (China)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; PROCESS DEVELOPMENT; THROUGH-SI VIA;

SILICON WAFERS;

ELECTROPLATING;

EID: 77955197306     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2010.5490740     Document Type: Conference Paper

References (4)

1. ITRS 2007, http://www.itrs.net/Links/2007ITRS/Home200.htm
2. D.Y. Chen, et. al "Enabling 3D-IC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking" IEDM Tech. Dig., 2009, p. 353
3. "IMEC Research Energetically Stacks Up", http://www.electroiq. com/index/display/packagingarticle- display/346388/s-articles/s- advancedpackaging/ s-volume-17/s-issue-11/s-departments/s-inthe-news/s-imec- research-energetically-stacks-up.html#
4. H. Y. Li, et. al " Built-in Via module test structure for backend interconnection in line process monitor", IPFA 2005 proceeding P.167-170