메뉴 건너뛰기




Volumn , Issue , 2008, Pages

Through-silicon via and die stacking technologies for microsystems- integration

Author keywords

[No Author keywords available]

Indexed keywords


EID: 64549150493     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796734     Document Type: Conference Paper
Times cited : (70)

References (8)
  • 1
    • 2442641371 scopus 로고    scopus 로고
    • 3D Interconnection and packaging: Impending reality or still a dream?
    • 15-19 February, San Francisco, CA, pp
    • E.Beyne, "3D Interconnection and packaging: impending reality or still a dream?" IEEE ISSCC2004, 15-19 February 2004; San Francisco, CA, pp.138-145.
    • (2004) IEEE ISSCC2004 , pp. 138-145
    • Beyne, E.1
  • 2
    • 0035714371 scopus 로고    scopus 로고
    • Technologies for very high bandwidth electrical interconnects between next generation VLSI circuits
    • December 2-5, Washington, D.C
    • E.Beyne, "Technologies for very high bandwidth electrical interconnects between next generation VLSI circuits", IEEE-IEDM 2001 Technical Digest, December 2-5, Washington, D.C., S23-p3, 2001.
    • (2001) IEEE-IEDM 2001 Technical Digest
    • Beyne, E.1
  • 3
    • 50249088167 scopus 로고    scopus 로고
    • The rise of the 3rd dimension for system integration
    • 5-7 July, San Francisco, CA, USA
    • E.Beyne, "The rise of the 3rd dimension for system integration", IEEE-IITC, 5-7 July 2006, San Francisco, CA, USA, 2006, 1-5.
    • (2006) IEEE-IITC , pp. 1-5
    • Beyne, E.1
  • 4
    • 0033718159 scopus 로고    scopus 로고
    • The indent reflow sealing (IRS) technique-a method for the fabrication of sealed cavities for MEMS devices
    • June
    • H.A.C. Tilmans, M. van de Peer, E. Beyne, The indent reflow sealing (IRS) technique-a method for the fabrication of sealed cavities for MEMS devices, Journal of Microelectromechanical Systems, Vol. 9, 2, June 2000, pp. 206 - 217
    • (2000) Journal of Microelectromechanical Systems , vol.9 , Issue.2 , pp. 206-217
    • Tilmans, H.A.C.1    van de Peer, M.2    Beyne, E.3
  • 7
    • 64549127115 scopus 로고    scopus 로고
    • Cost effective 3D-system integration using through-silicon-via technologies
    • 7 December, Makuhari, Japan, S9P1
    • E.Beyne, "Cost effective 3D-system integration using through-silicon-via technologies", Semi Technology Symposium, 7 December 2007, Makuhari, Japan, 2007, S9P1.
    • (2007) Semi Technology Symposium
    • Beyne, E.1
  • 8
    • 35348819915 scopus 로고    scopus 로고
    • Sloped through wafer vias for 3D Wafer Level packaging
    • May 29-June 1, Reno, NV, USA
    • D. Sabuncuoglu Tezcan et al "Sloped through wafer vias for 3D Wafer Level packaging", Proc. 57th IEEE ECTC 2007, May 29-June 1, Reno, NV, USA, 2007.
    • (2007) Proc. 57th IEEE ECTC
    • Sabuncuoglu Tezcan, D.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.