Edge Separability-Based Circuit Clustering with Application to Multilevel Circuit Partitioning

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 23, Issue 3, 2004, Pages 346-357

  Cong, Jason ^a   Lim, Sung Kyu ^b  

^a University of California   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Clustering; Edge separability; Multilevel partitioning

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; EDGE DETECTION; INTERPOLATION; OPTIMIZATION; PARAMETER ESTIMATION; PARTIAL DIFFERENTIAL EQUATIONS; VLSI CIRCUITS;

EDGE SEPARABILITY-BASED CLUSTERING (ESC); MULTILEVEL CIRCUIT PARTITIONING;

INTEGRATED CIRCUIT LAYOUT;

EID: 1642336365     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2004.823353     Document Type: Article

References (41)

1. A. V. Goldberg and R. E. Tarjan, "A new approach to the maximum flow problem," J. ACM, pp. 921-940, 1988.
2. H. Nagamochi and T. Ibaraki, "Computing edge-connectivity in multigraphs and capacitated graphs," SIAM J. Discrete Math., pp. 54-66, 1992.
3. W. Sun and C. Sechen, "Efficient effective placements for very large circuits," in Proc. IEEE Int. Conf. Computer-Aided Design, 1993, pp. 170-177.
4. J. Cong and M. Smith, "A parallel bottom-up clustering algorithm with applications to circuit partitioning VLSI design," in Proc. ACM Design Automation Conf., 1993, pp. 755-760.
5. D. J. Huang and A. B. Kahng, "When clusters meet partitions: New density-based methods for circuit decomposition," in Proc. Eur. Design Test Conf., 1995, pp. 60-64.
6. T. K. Ng, J. Oldfield, and V. Pitchumani, "Improvements of a mincut partition algorithm," in Proc. IEEE Int. Conf. Computer-Aided Design, 1987, pp. 470-473.
7. Y. C. Wei and C. K. Cheng, "Ratio cut partitioning for hierarchical designs," IEEE Trans. Computer-Aided Design, vol. 10, pp. 911-921, July 1991.
8. H. Shin and C. Kim, "A simple yet effective technique for partitioning," IEEE Trans. VLSI Syst., vol. 12, pp. 380-386, Sept. 1993.
9. D. M. Schuler and E. G. Ulrich, "Clustering and linear placement," in Proc. ACM Design Automation Conf., 1972, pp. 50-56.
10. G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar, "Multilevel hypergraph partitioning: Application in VLSI domain," in Proc. ACM Design Automation Conf., 1997, pp. 526-529.
11. G. Karypis and V. Kumar, "Multilevel k-way hypergraph partitioning," in Proc. ACM Design Automation Conf., 1999.
12. T. Chan, J. Cong, T. Kong, and J. Shinnel, "Multilevel optimization for large-scale circuit placement," in Proc. IEEE Int. Conf. Computer-Aided Design, 2000, pp. 171-176.
13. K. Nabors and J. White, "Fastcap: A multipole accelerated 3-D capacitance extraction program," IEEE Trans. Computer-Aided Design, vol. 10, pp. 1447-1459, Nov. 1991.
14. M. Edahiro and T. Yoshimura, "New placement and global routing algorithms for standard cell layouts," in Proc. ACM Design Automation Conf., 1990, pp. 642-645.
15. J. Cong and Y. Ding, "On area/depth trade-off in LUT-based FPGA technology mapping," in Proc. ACM Design Automation Conf., 1993, pp. 213-218.
16. J. Cong, H. P. Li, S. K. Lim, T. Shibuya, and D. Xu, "Large scale circuit partitioning with loose/stable net removal and signal flow based clustering," in Proc. IEEE Int. Conf. Computer-Aided Design, 1997, pp. 441-446.
17. E. L. Lawler, K. N. Levitt, and J. Turner, "Module clustering to minimize delay in digital networks," IEEE Trans. Computer-Aided Design, vol. C-18, pp. 47-57, Jan. 1966.
18. R. Murgai, R. K. Brayton, and A. S. Vincentelli, "On clustering for minimum delay/area," in Proc. IEEE Int. Conf. Computer-Aided Design, vol. 10, Jan. 1991, pp. 6-9.
19. R. Rajaraman and D. F. Wong, "Optimal clustering for delay minimization," in Proc. ACM Design Automation Conf., 1993, pp. 309-314.
20. H. Yang and D. F. Wong, "Circuit 'clustering for delay minimization under area and pin constraints," in Proc. Eur. Design Test Conf., 1995, pp. 65-70.
21. P. Pan, A. K. Karandikar, and C. L. Liu, "Optimal clock period clustering for sequential circuits with retiming," IEEE Trans. Computer-Aided Design, vol. 17, pp. 489-498, June 1998.
22. J. Cong, H. Li, and C. Wu, "Simultaneous circuit partitioning/clustering with retiming for performance optimization," in Proc. ACM Design Automation Conf., 1999, pp. 460-465.
23. J. Cong, S. K. Lim, and C. Wu, "Performance driven multi-level and multiway partitioning with retiming," in Proc. ACM Design Automation Conf., 2000, pp. 274-279.
24. S. Hauck and G. Borriello, "An evaluation of bipartitioning techniques," in Proc. Conf. Adv. Res. VLSI, 1995, pp. 383-402.
25. C. J. Alpert, L. W. Hagen, and A. B. Kahng, "A hybrid multilevel/genetic approach for circuit partitioning," in Proc. ACM/SIGDA Phys. Design Workshop, 1996, pp. 100-105.
26. C. J. Alpert, D. Huang, and A. B. Kahng, "Multilevel circuit partitioning," in Proc. ACM Design Automation Conf., 1997, pp. 530-533.
27. J. Cong and S. K. Lim, "Performance driven multiway partitioning," in Proc. Asia South Pacific Design Automation Conf., 2000, pp. 441-446.
28. _, "Edge separability-based circuit clustering with application to circuit partitioning," in Proc. Asia South Pacific Design Automation Conf., 2000, pp. 429-434.
29. _, "Physical planning with retiming," in Proc. IEEE Int. Conf. Computer-Aided Design, 2000, pp. 2-7.
30. C. J. Alpert and A. B. Kahng, "Recent directions in netlist partitioning: a survey," Integration, VLSI J., pp. 1-81, 1995.
31. L. R. Ford and D. R. Fulkerson, Flows in Networks. Princeton, NJ: Princeton Univ. Press, 1962.
32. C. J. Alpert and A. B. Kahng, "A general framework for vertex ordering with applications to netlist clustering," in Proc. IEEE Int. Conf. Computer-Aided Design, 1994, pp. 652-657.
33. H. Nagamochi and T. Ibaraki, "Linear time algorithm for finding a sparse k-connected spanning subgraph of a fe-connected graph," Algorithmica, pp. 583-596, 1992.
34. A. Frank, "On the Edge Connectivity Algorithm of Nagamochi and Ibaraki," Labaratoire Artemis, IMAO, Université J. Fourier, Grenoble, France, Tech. Rep. 1994.
35. S. Fujishige, "Another simple proof of the validity of Nagamochi and Ibaraki's minimum cut algorithm and Queyrannes extension to symmetric submodular function minimization," Forschungsinstitut für Diskrete Math., Univ. Bonn, Bonn, Germany, Tech. Rep. 1994.
36. M. Stoer and F. Wagner, "A simple min cut algorithm," in Proc. Eur. Symp. Algorithms, Lecture Notes Comput. Sci., vol. 855, 1994, pp. 141-147.
37. C. J. Alpert, "The ISPD98 circuit benchmark suite," in Proc. Int. Symp. Phys. Design, 1998, pp. 80-85.
38. E. A. Dinic, "Algorithm for solution of a problem of maximum flow in networks with power estimation," Soviet Math. Dokl., pp. 1277-1280, 1970.
39. C. Fiduccia and R. Mattheyses, "A linear time heuristic for improving network partitions," in Proc. ACM Design Automation Conf., 1982, pp. 175-181.
40. C. Alpert. (1999). [Online]. Available: http://vlsicad.cs.ucla.edu/~cheese/errata.html
41. J. Cong and S. K. Lim, "Multiway partitioning with pairwise movement," in Proc. IEEE Int. Conf. Computer-Aided Design, 1998, pp. 512-516.