A multilevel analytical placement for 3D ICs

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2009, Pages 361-366

  Cong, Jason ^a,b   Luo, Guojie ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b CALIFORNIA NANOSYSTEMS INSTITUTE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D ICS; A DENSITIES; ANALYTICAL PLACEMENTS; AREA DENSITIES; DEVICE LAYERS; DISCRETE LAYERS; NON-LINEAR PROGRAMMING; PENALTY FUNCTIONS; PLACEMENT METHODS; VIA DENSITIES; WEIGHTED SUMS; WIRE LENGTHS; Z DIRECTIONS;

COMPUTER AIDED DESIGN; LINEARIZATION; UNMANNED AERIAL VEHICLES (UAV);

DIGITAL INTEGRATED CIRCUITS;

EID: 64549106487     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2009.4796507     Document Type: Conference Paper

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