Overview and Scaling Prospect of Ferroelectric Memories

Analog Circuits and Signal Processing

Volumn , Issue , 2010, Pages 361-380

  Takashima, Daisaburo ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

Chain FeRAM; FeRAM; Ferroelectric; Memory; RAM

Indexed keywords

CAPACITANCE; CHAINS; CYTOLOGY; FERROELECTRIC DEVICES; FERROELECTRIC RAM; FERROELECTRICITY;

CELL STRUCTURE; CHAIN FERROELECTRIC RANDOM ACCESS MEMORY; FERROELECTRIC MEMORY; FERROELECTRIC RANDOM ACCESS MEMORY; MEMORY CELL; OPERATING CURRENTS; OPERATING PRINCIPLES; SCALINGS; STRUCTURE MATERIALS;

CELLS;

EID: 84863991174     PISSN: 1872082X     EISSN: 21971854     Source Type: Book Series    
DOI: 10.1007/978-90-481-9216-8_12     Document Type: Chapter

References (35)

1. J.T. Evans, R. Womack, An experimental 512-bit nonvolatile memory with ferroelectric storage cell. IEEE J. Solid State Circuits 23(5), 1171–1175 (Oct 1989)
2. R. Womack, D. Tolsch, A 16kb ferroelectric nonvolatile memory with a bit parallel architecture, in ISSCC Dig. Tech. Papers, Feb 1989, pp. 242–243
3. T. Sumi, N. Moriwaki, G. Nakane, T. Nakakuma, Y. Judai, Y. Uemoto, Y. Nagano, S. Hayashi, M. Azuma, E. Fujii, S. I. Katsu, T. Otsuki, L. McMillan, C. Paz de Araujo G. G. Kano, A 256kb nonvolatile ferroelectric memory at 3V and 100ns, in ISSCC Dig. Tech. Papers, Feb 1994, pp. 268–269
4. H.P. McAdams, R. Acklin, T. Blake, X.H. Du, J. Eliason, J. Fong, W. F. Kraus, D. Liu, S. Madan, T. Moise, S. Natarajan, N. Qian, Y. Qiu, K.A. Remack, J. Rodriguez, J. Roscher, A. Seshadri, S.R. Summerfelt. A 64-Mb embedded FRAM utilizing a 130-nm 5LM Cu/FSG logic process. IEEE J. Solid Sate Circuits 39(4), 1625–1634, 667–677 (Apr 2004)
5. 2, 1T1C FRAM cell for SoC (system-on-a-chip)-friendly applications, in Symposium on VLSI Technology Dig. Tech. Papers, June 2007, pp. 230–231
6. K. Hoya, D. Takashima, S. Shiratake, R. Ogiwara, T. Miyakawa, H. Shiga, S.M. Doumae, S. Ohtsuki, Y. Kumura, S. Syuto, T. Ozaki, K. Yamakawa, I. Kunishima, A. Nitayama, S. Fujii, A 64Mb chain FeRAM with quad BL architecture and 200MB/s burst mode, in ISSCC Dig. Tech. Papers, Feb 2006, pp. 134–135
7. H. Shiga, D. Takashima, S. Shiratake, K. Hoya, T. Miyakawa, R. Ogiwara, R. Fukuda, R. Takizawa, K. Hatsuda, F. Matsuoka, Y. Nagadomi, D. Hashimoto, H. Nishimura, T. Hioka, S. Doumae, S. Shimizu, M. Kawano, T. Taguchi, Y. Watanabe, S. Fujii, T. Ozaki, H. Kanaya, Y. Kumura, Y. Shimojo, Y. Yamada, Y. Minami, S. Shuto, K. Yamakawa, S. Yamazaki, I. Kunishima, T. Hamamoto, A. Nitayama, T. Furuyama, A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes. IEEE J. Solid State Circuits 45(5), 141–152 (Jan 2010)
8. D. Takashima, I. Kunishima, M. Noguchi, S. Takagi, High-density chain ferroelectric random-access memory (CFRAM), in Symposium on VLSI Circuits Dig. Tech. Papers, June 1997, pp. 83–84
9. D. Takashima, I. Kunishima, High-density chain ferroelectric random access memory (chain FRAM). IEEE J. Solid State Circuits 33(5), 787–792 (May 1998)
10. H. Masuda, R. Hori, R. Kamigaki, K. Itoh, H. Kawamoto, H. Hatto, A 5V-only 64 dynamic RAM based on high S/N design. IEEE J. Solid State Circuits 15(5), 846–854 (Oct 1980)
11. S. Onishi, K. Hamada, K Ishihara, Y. Ito, S. Yokoyama, J. Kudo, K. Sakiyama, A half-micron ferroelectric memory cell technology with stacked capacitor structure, in IEDM Dig. Tech. Papers, Dec 1994, pp. 843–846
12. 2 Vcc/2-plate nonvolatile DRAM cell with Pt/PZT/Pt/TiN capacitor patterned by one-mask dry etching, in Symposium on VLSI Technology Dig. Tech. Papers, June 1996, pp. 28–29
13. Y. Shimojo, A. Konno, J. Nishimura, T. Okada, Y. Yamada, S. Kitazaki, H. Furuhashi, S. Yamazaki, K. Yahashi, K. Tomioka, Y. Minami, H. Kanaya, S. Shuto, K. Yamakawa, T. Ozaki, H. Shiga, T. Miyakawa, S. Shiratake, D. Takashima, I. Kunishima, T. Hamamoto, A. Nitayama. High-density and high-speed 128Mb chain FeRAM with SDRAM-Compatible DDR2 Interface, in Symposium on VLSI Technology Dig. Tech. Papers, June 2009, pp. 218–219
14. D. Takashima, S. Shuto, I. Kunishima, H. Takenaka, Y. Oowaki, S. Tanaka, A sub-40ns chain FRAM architecture with 7ns cell-plateline drive. IEEE J. Solid State Circuits 34(11), 1557–1563 (Nov 1999)
15. D. Takashima, Y. Takeuchi, T. Miyakawa, Y. Itoh, R. Ogiwara, M. Kamoshida, K. Hoya, S.M. Doumae, T. Ozaki, H. Kanaya, K. Yamakawa, I. Kunishima, Y. Oowaki, A 76-mm2 8-Mb chain ferroelectric memory. IEEE J. Solid State Circuits 36(11), 1713–1720 (Nov 2001)
16. S. Shiratake, T. Miyakawa, Y. Takeuchi, R. Ogiwara, M. Kamoshida, K. Hoya, K. Oikawa, T. Ozaki, I. Kunishima, K. Yamakawa, S. Sugimoto, D. Takashima, H.O. Joachim, N. Rehm, J. Wohlfahrt, N. Nagel, G. Beitel, M. Jacob, T. Roehr, A 32-Mb chain FeRAM with segment/ stitch array architecture. IEEE J. Solid State Circuits 38(11), 1911–1919 (Nov 2003)
17. T. Ozaki, N. Nagel, Y. Kumura, J. Lian, A. Hilliger, T. Tsuchiya, R. Bruchhaus, H. Kanaya, H. Koyama, U. Wellhausen, O. Hidaka, S. Shuto, S. Gemhardt, Y. Shimojo, B. K. Moon, H. Itokawa, U. Egger, H. Zhuang, K. Tomioka, M. Fukushima, K. Yamakawa, D. Takashima, I. Kunishima, Y. Oowaki, G. Beitel, Key technologies of first chain – 32Mbit ferroelectric RAM, in Extended Abstract of SSDM, Sept 2003, pp. 646–647
18. 2 nestled chain cell structure formed by one mask etching process for 64Mbit FeRAM, in Symposium on VLSI Technology Dig. Tech. Papers, June 2004, pp. 150–151
19. J. Yamada, T. Miwa, H. Koike, H. Toyoshima, K. Amanuma, S. Kobayashi, T. Tatsumi, Y. Maejima, H. Hada, H. Mori, S. Takahashi, H. Takeuchi, T. Kunio, A 128-kb FeRAM macro for contact/contactless smart-card microcontrollers. IEEE J. Solid State Circuits 37(8), 1073–1079 (Aug 2002)
20. D. Takashima, Y. Oowaki, I. Kunishima, Gain cell block architecture for gigabit-scale chain ferroelectric RAM, in Symposium on VLSI Circuits Dig. Tech. Papers, June 1999, pp. 103–104
21. R. Ogiwara, S. Tanaka, Y. Itoh, T. Miyakawa, Y. Takeuchi, S. Doumae, H. Takenaka, I. Kunishima, S. Shuto, O. Hidaka, S. Ohtsuki, A 0.5 mm 3V 1T1C FRAM with a variable reference bitline voltage scheme using a fatigue free reference capacitor. IEEE J. Solid State Circuits 34(4), 545–551 (Apr 2000)
22. 2 1Mb nonvolatile ferroelectric memory utilizing advanced architecture for enhanced reliability, in Symposium on VLSI Circuits Dig. Tech. Papers, June 1998, pp. 242–243
23. H.B. Kang, H.W. Kye, D.J. Kim, G.I. Lee, J.H. Park, J.K. Wee, S.S. Lee, S.K. Hong, N.S. Kang, J.Y. Chung, A pulse-tuned charge controlling scheme for uniform main and reference bitline voltage generation on 1T1C FeRAM, in Symposium on VLSI Circuits Dig. Tech. Papers, June 2001, pp. 125–126
24. H. Koike, T. Otsuki, T. Kimura, M. Fukuma, Y. Hayashi, Y. Maejima, K. Amantuma, N. Tanabe, T. Masuki, S. Saito, T. Takeuchi, S. Kobayashi, T. Kunio, T. Hase, Y. Miyasaka, N. Shohata, M. Takada, A 60 ns 1Mb nonvolatile ferroelectric memory with non-driven cell plate line write/read scheme, in ISSCC Dig. Tech. Papers, Feb 1996, pp. 268–269
25. S. Kawashima, T. Endo, A. Yamamoto, K. Nakabayashi, M. Nakazawa, K. Morita, M. Aoki, Bitline GND sensing technique for low-voltage operation FeRAM. IEEE J. Solid State Circuits 37(5), 591–598 (May 2002)
26. D. Takashima, H. Shiga, T. Miyakawa, S. Shiratake, K. Hoya, R. Ogiwara, R. Takizawa, S. Doumae, R. Fukuda, Y. Watanabe, S. Fujii, T. Ozaki, H. Kanaya, S. Shuto, K. Yamakawa, I. Kunishima, T. Hamamoto, A. Nitayama, A scalable shield-bitline-overdrive technique for 1.3 V chain FeRAM, in ISSCC Dig. Tech. Papers, Feb 2010, pp. 262–263
27. Y. Kumura, T. Ozaki, H. Kanaya, O. Hidaka, Y. Shimojo, S. Shuto, Y. Yamada, K. Tomioka, K. Yamakawa, S. Yamazaki, D. Takashima, T. Miyakawa, S. Shiratake, S. Ohtsuki, I. Kunishima, A. Nitakaya, A SrRuO3/IrO2 top electrode FeRAM with Cu BEOL process for embedded memory of 130 nm generation and beyond. Solid State Electron. 50(4), 606–612 (Apr 2006)
28. J.M. Koo, B.S. Seo, S. Kim, S. Shin, J.H. Lee, H. Baik, J.H. Lee, J.H. Lee, B.J. Bae, J.E. Lim, D.C. Yoo, S.O. Park, H.S. Kim, H. Han, S. Baik, J.Y. Choi, Y.J. Park, Y. Park, Fabrication of 3D trench PZT capacitors for 256Mbit FRAM device application, in IEDM Dig. Tech. Papers, Dec 2005, pp. 340–343
29. N. Nagel, R. Bruchhaus, K. Homik, U. Egger, H. Zhuang, H.-O. Joachim, T. Rohr, G Beitel T. Ozaki, I. Kunishima, New highly scalable 3 dimensional chain FeRAM cell with vertical capacitor, in Symposium on VLSI Technology Dig. Tech. Papers, June 2004, pp. 146–147
30. T. Nishihara, Y. Ito, A Quasi-matrix ferroelectric memory for future silicon storage. IEEE J. Solid State Circuits 37(11), 1479–1484 (Nov 2002)
31. J.L. Moll, Y. Tarui, A new solid state memory resistor. IEEE Electron Dev. ED-10, 338–339 (Sept 1963)
32. T. Nakamura, Y. Nakao, A. Kamisawa, H.Takasu, A single-transistor ferroelectric memory cell, in ISSCC Dig. Tech. Papers, Feb 1995, pp. 68–69
33. S. Sakai, M. Takahashi, K. Takeuchi, Q.H. Li, T. Horiuchi, S. Wang, K.Y. Yun, M. Takamiya, T. Sakurai, Highly scalable Fe(ferroelectric)-NAND cell with MFIS (metal-ferroelectric-insulator-semiconductor) structure for sub-10nm Tera-bit capacity NAND flash memories, in NVSMW Dig. Tech. Papers, May 2008, pp. 103–105
34. D. Takashima, NAND flash memory and system designs for SSD application, in Forum of SSD Memory Subsystem Innovation, ISSCC, Feb 2009
35. D. Takashima, Y. Nagadomi, K. Hatsuda, Y. Watanabe, S. Fujii, A 128Mb chain FeRAM and system designs for HDD application and Enhanced HDD performance, in A-SSCC Dig. Tech. Papers, Nov 2009, pp. 13–16