A 0.5-μm, 3-V, 1T1C, 1-Mbit FRAM with a Variable Reference Bit-Line Voltage Scheme using a Fatigue-Free Reference Capacitor

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 4, 2000, Pages 545-551

  Ogiwara, Ryu ^a   Tanaka, Sumio ^a   Itoh, Yasuo ^a   Miyakawa, Tadashi ^a   Takeuchi, Yoshiaki ^a   Doumae, Sumiko Mano ^a   Takenaka, Hiroyuki ^a   Kunishima, Iwao ^a   Shuto, Susumu ^a   Hidaka, Osamu ^a   Ohtsuki, Sumito ^a   Tanaka, Shin Ichi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

1 Mbit; double wordline pulse; FRAM; variable reference voltage

Indexed keywords

EID: 85008006251     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.839914     Document Type: Article

References (5)

1. W. Kinney,Integ. Ferroelect., vol. 4, pp. 131-144, 1994.
2. S. Tanaka, R. Ogiwara, Y. Itoh, T. Miyakawa, Y. Takeuchi, S. Doumae, H. Takenaka, and H. Kamata, “FRAM cell design with high immunity to fatigue and imprint for 0.5 µm 3 V 1T1C 1M bit FRAM,” in IEDM Tech. Dig., 1998, pp. 359-362.
3. T. Miyakawa, S. Tanaka, Y. Itoh, Y. Takeuchi, R. Ogiwara, S. Doumae, H. Takenaka, I. Kunishima, S. Shuto, O. Hidaka, O. Ohtsuki, and S. Tanaka, “A 0.5 µm 3v 1T1C 1Mb FRAM with avariable reference bitline voltage scheme using a fatigue-free reference capacitor,” in ISSCC Dig. Tech. Papers, 1999, pp. 104-105.
4. R. L. Geiger, P. E. Allen, and N. R. Strader,VLSI Design Techniques for Analog and Digital Circuits. New York: McGraw-Hill, pp. 623-626.
5. S. Tanaka, R. Ogiwara, Y. Itoh, T. Miyakawa, Y. Takeuchi, S. Doumae, H. Takenaka, and H. Kamata, “FRAM cell design with high immunity to fatigue and imprint for 0.5 µm 3 V 1T1C 1M bit FRAM,” IEEE Trans. Electron Devices, to be published.