Gain cell block architecture for gigabit-scale chain ferroelectric RAM

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1999, Pages 103-104

  Takashima, D ^a   Oowaki, Y ^a   Kunishima, I ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CAPACITORS; DATA STORAGE EQUIPMENT; ELECTRIC POTENTIAL; FERROELECTRIC DEVICES; POLARIZATION; TRANSISTORS;

BITLINES; CELL POLARIZATION; GAIN CELL BLOCK ARCHITECTURE; GAIN TRANSISTOR; GIGABIT SCALE CHAIN FERROELECTRIC RAM; LOAD CAPACITANCE; MEMORY CELL; WORDLINES;

RANDOM ACCESS STORAGE;

EID: 0033281315     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)