A scalable shield-bitline-overdrive technique for 1.3V chain FeRAM

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 262-263

  Takashima, Daisaburo ^a   Shiga, Hidehiro ^a   Hashimoto, Daisuke ^a   Miyakawa, Tadashi ^a   Shiratake, Shinichiro ^a   Hoya, Katsuhiko ^a   Ogiwara, Ryu ^a   Takizawa, Ryosuke ^a   Doumae, Sumiko ^a   Fukuda, Ryo ^a   Watanabe, Yohji ^a   Fujii, Shuso ^a   Ozaki, Tohru ^a   Kanaya, Hiroyuki ^a   Shuto, Susumu ^a   Yamakawa, Koji ^a   Kunishima, Iwao ^a   Hamamoto, Takeshi ^a   Nitayama, Akihiro ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

BIT LINES; CELL SIGNALS; DEVICE-SCALING; FERRO-ELECTRIC RAMS; FERROELECTRIC CAPACITORS; LOW VOLTAGE OPERATION; MEMORY CAPACITY; MEMORY SYSTEMS; NAND FLASH MEMORY; NON-VOLATILE RAMS; OVERDRIVE TECHNIQUE; PROGRAM/ERASE; READ OPERATION;

CAPACITANCE; CAPACITORS; FERROELECTRIC DEVICES; FERROELECTRICITY; FLASH MEMORY; HARD DISK STORAGE; MICROPROCESSOR CHIPS; RANDOM ACCESS STORAGE;

CACHE MEMORY;

EID: 77952128336     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433950     Document Type: Conference Paper

References (6)

1. D. Takashima et al., "High-density chain ferroelectric random access memory (chain FRAM)," IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 787-792, May 1998.
2. D. Takashima, et al., "A 128Mb chain FeRAM and system designs for HDD application and enhanced HDD performance", A-SSCC Dig. Tech. Papers, Nov., 2009, to be published.
3. D. Takashima, "NAND flash memory and system designs for SSD application," ISSCC forum of " SSD Memory Subsystem Innovation", Feb. , 2009.
4. H. Shiga et al., "A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bit-line and sensing schemes," ISSCC Dig. Tech. Papers, pp.464-465, Feb., 2009.
5. K. Hoya et al., "A 64Mb chain FeRAM with quad BL architecture and 200MB/s burst mode," ISSCC Dig. Tech. Papers, pp.134-135, Feb., 2006.
6. 2 8-Mb chain ferroelectric memory," IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 1713-1720, Nov., 2001.