Sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 11, 1999, Pages 1557-1563

  Takashima, Daisaburo ^a   Shuto, Susumu ^a   Kunishima, Iwao ^a   Takenaka, Hiroyuki ^a   Oowaki, Yukihito ^a,b   Tanaka, Shin Ichi ^a  

^a TOSHIBA CORPORATION   (Japan)

^b UNIVERSITY OF CAMBRIDGE   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CAPACITORS; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; ELECTRIC NETWORK ANALYSIS; FERROELECTRIC DEVICES; MAGNETIC DISK STORAGE; MICROPROCESSOR CHIPS; NONVOLATILE STORAGE; TRANSISTORS;

CELL-PLATE-LINE DRIVES; NONVOLATILE CHAIN FERROELECTRIC RANDOM ACCESS MEMORY (FRAM);

RANDOM ACCESS STORAGE;

EID: 0033221853     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.799863     Document Type: Article

References (8)

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3. cc/2-plate nonvolatile DRAM cell with Pt/PZT/Pt/TiN capacitor patterned by one-mask dry etching," in Symp. VLSI Technology Dig. Tech. Papers, June 1996, pp. 28-29.
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8. D. Takashima, S. Shuto, I. Kunishima, H. Takenada, Y. Oowaki, and S. Tanaka, "A sub-40 ns random-access chain FRAM architecture with a 7 ns cell-plate-line drive," in ISSCC Dig. Tech. Papers, Feb. 1999, pp. 102-103.