-
1
-
-
18244414879
-
Demonstration of a 4 Mb, high density ferroelectric memory embedded within a 130 nm, 5LM Cu/FSG logic process
-
T. S. Moise et al., "Demonstration of a 4 Mb, high density ferroelectric memory embedded within a 130 nm, 5LM Cu/FSG logic process," in IEDM Tech. Dig., 2002, pp. 535-538.
-
(2002)
IEDM Tech. Dig.
, pp. 535-538
-
-
Moise, T.S.1
-
2
-
-
17644435882
-
2) Ir/PZT/Ir capacitors formed on W plugs
-
2) Ir/PZT/Ir capacitors formed on W plugs," in IEDM Tech. Dig., 1999, pp. 940-942.
-
(1999)
IEDM Tech. Dig.
, pp. 940-942
-
-
Moise, T.S.1
-
3
-
-
0035842769
-
2) Pb(Zr,Ti)O3 capacitors on W plugs with Al interconnect
-
2) Pb(Zr,Ti)O3 capacitors on W plugs with Al interconnect," Appl. Phys. Lett., vol. 79, pp. 4004-4006, 2001.
-
(2001)
Appl. Phys. Lett.
, vol.79
, pp. 4004-4006
-
-
Summerfelt, S.R.1
-
4
-
-
0141610314
-
A novel sense-amplifier and plate-line architecture for ferroelectric memories
-
J. T. Rickes et al., "A novel sense-amplifier and plate-line architecture for ferroelectric memories," Integrat. Ferroelectr., vol. 48, pp. 109-118, 2002.
-
(2002)
Integrat. Ferroelectr.
, vol.48
, pp. 109-118
-
-
Rickes, J.T.1
-
5
-
-
33646909695
-
A survey of circuit innovations in ferroelectric random-access memories
-
May
-
A. Sheikholeslami and P. G. Gulak, "A survey of circuit innovations in ferroelectric random-access memories," Proc. IEEE, vol. 88, pp. 667-689, May 2000.
-
(2000)
Proc. IEEE
, vol.88
, pp. 667-689
-
-
Sheikholeslami, A.1
Gulak, P.G.2
-
6
-
-
0031381785
-
Modeling ferroelectric capacitor switching using a parallel-elements model
-
B. Jiang, J. C. Lee, P. Zurcher, and R. E. Jones Jr., "Modeling ferroelectric capacitor switching using a parallel-elements model," Integrat. Ferroelectr., vol. 16, pp. 199-208, 1997.
-
(1997)
Integrat. Ferroelectr.
, vol.16
, pp. 199-208
-
-
Jiang, B.1
Lee, J.C.2
Zurcher, P.3
Jones Jr., R.E.4
-
7
-
-
0030681625
-
Computationally efficient ferroelectric capacitor model for circuit simulation
-
June
-
B. Jiang, P. Zurcher, R. E. Jones, S. J. Gillespie, and J. C. Lee, "Computationally efficient ferroelectric capacitor model for circuit simulation," in Symp. VLSI Technology Dig. Tech. Papers, June 1997, pp. 141-142.
-
(1997)
Symp. VLSI Technology Dig. Tech. Papers
, pp. 141-142
-
-
Jiang, B.1
Zurcher, P.2
Jones, R.E.3
Gillespie, S.J.4
Lee, J.C.5
-
8
-
-
0031634420
-
2 1 Mb nonvolatile ferroelectric memory utilizing advanced architecture for enhanced reliability
-
June
-
2 1 Mb nonvolatile ferroelectric memory utilizing advanced architecture for enhanced reliability," in Symp. VLSI Circuits Dig. Tech. Papers, June 1998, pp. 242-245.
-
(1998)
Symp. VLSI Circuits Dig. Tech. Papers
, pp. 242-245
-
-
Kraus, W.1
Lehman, L.2
Wilson, D.3
Yamazaki, T.4
Ohno, C.5
Nagai, E.6
Yamazaki, H.7
Suzuki, H.8
-
9
-
-
0001443688
-
A 0.5 μm 3 V 1T1C 1 Mb FRAM with a variable reference bitline voltage scheme using a fatigue-free reference capacitor
-
Feb.
-
T. Miyakawa, S. Tanaka, Y. Itoh, Y. Takeuchi, R. Ogiwara, S. M. Doumae, H. Takenaka, I. Kunishima, S. Shuto, O. Hidaka, S. Ohtsuki, and S. Tanaka, "A 0.5 μm 3 V 1T1C 1 Mb FRAM with a variable reference bitline voltage scheme using a fatigue-free reference capacitor," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, vol. 42, Feb. 1999, pp. 104-105.
-
(1999)
IEEE Int. Solid-state Circuits Conf. Dig. Tech. Papers
, vol.42
, pp. 104-105
-
-
Miyakawa, T.1
Tanaka, S.2
Itoh, Y.3
Takeuchi, Y.4
Ogiwara, R.5
Doumae, S.M.6
Takenaka, H.7
Kunishima, I.8
Shuto, S.9
Hidaka, O.10
Ohtsuki, S.11
Tanaka, S.12
-
10
-
-
0034316380
-
A 0.4-μm 3.3-V 1T1C 4-Mb nonvolatile ferroelectric RAM with fixed bitline reference voltage scheme and data protection circuit
-
Nov.
-
B. Jeon, M. Choi, Y. Song, S. Oh, Y. Chung, K. Suh, and K. Kim, "A 0.4-μm 3.3-V 1T1C 4-Mb nonvolatile ferroelectric RAM with fixed bitline reference voltage scheme and data protection circuit," IEEE J. Solid-State Circuits, vol. 35, pp. 1690-1694, Nov. 2000.
-
(2000)
IEEE J. Solid-state Circuits
, vol.35
, pp. 1690-1694
-
-
Jeon, B.1
Choi, M.2
Song, Y.3
Oh, S.4
Chung, Y.5
Suh, K.6
Kim, K.7
-
11
-
-
0031640944
-
A self-reference read scheme for a 1T/1C FeRAM
-
June
-
J. Yamada, T. Miwa, H. Koike, and H. Toyoshima, "A self-reference read scheme for a 1T/1C FeRAM," in Symp. VLSI Circuits Dig. Tech. Papers, June 1998, pp. 238-241.
-
(1998)
Symp. VLSI Circuits Dig. Tech. Papers
, pp. 238-241
-
-
Yamada, J.1
Miwa, T.2
Koike, H.3
Toyoshima, H.4
-
12
-
-
0029700792
-
The charge-share modified precharge-level (CSM) architecture for high-speed and low-power ferroelectric memory
-
June
-
H. Fujisawa, T. Sakata, T. Sekiguchi, O. Nagashima, K. Kimura, and K. Kajigaya, "The charge-share modified precharge-level (CSM) architecture for high-speed and low-power ferroelectric memory," in Symp. VLSI Circuits Dig. Tech. Papers, June 1996, pp. 50-51.
-
(1996)
Symp. VLSI Circuits Dig. Tech. Papers
, pp. 50-51
-
-
Fujisawa, H.1
Sakata, T.2
Sekiguchi, T.3
Nagashima, O.4
Kimura, K.5
Kajigaya, K.6
-
13
-
-
0034790370
-
A pulse-tuned charge controlling scheme for uniform main and reference bitline voltage generation on 1T1C FeRAM
-
June
-
H. Kang, H. Kye, D. Kim, G. Lee, J. Park, J. Wee, S. Lee, S. Hong, N. Kang, and J. Chung, "A pulse-tuned charge controlling scheme for uniform main and reference bitline voltage generation on 1T1C FeRAM," in Symp. VLSI Circuits Dig. Tech. Papers, June 2001, pp. 125-126.
-
(2001)
Symp. VLSI Circuits Dig. Tech. Papers
, pp. 125-126
-
-
Kang, H.1
Kye, H.2
Kim, D.3
Lee, G.4
Park, J.5
Wee, J.6
Lee, S.7
Hong, S.8
Kang, N.9
Chung, J.10
-
14
-
-
0141761422
-
A 64 Mb embedded FeRAM utilizing a 130 nm, 5LM Cu/FSG logic process
-
June
-
H. McAdams et al., "A 64 Mb embedded FeRAM utilizing a 130 nm, 5LM Cu/FSG logic process," in Symp. VLSI Circuits Dig. Tech. Papers, June 2003, pp. 175-176.
-
(2003)
Symp. VLSI Circuits Dig. Tech. Papers
, pp. 175-176
-
-
McAdams, H.1
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